公开(公告)号：US06712261B2

公开(公告)日：2004-03-30

申请号：US10102129

申请日：2002-03-20

Applicant: Richard R. Hall ,  How T. Lin ,  Christopher J. Majka ,  Matthew F. Seward ,  Ronald V. Smith

Inventor： Richard R. Hall ,  How T. Lin ,  Christopher J. Majka ,  Matthew F. Seward ,  Ronald V. Smith

IPC: B23K3102

CPC classification number: H01L21/486 ,  B23K1/20 ,  H05K3/4046 ,  H05K2201/10234 ,  H05K2201/10287

Abstract: An arrangement and method for the insertion the leading end of a length of a metallic element into a through hole which is formed in a substrate, and for heat deforming the inserted leading portion of the metallic element into a predetermined configuration prior to severing therefrom the remaining length of the metallic element.

Abstract translation: 一种用于将金属元件的长度的前端插入到形成在基板中的通孔中并且用于在将金属元件的插入的前导部分从其中切断之前将插入的前导部分变形为预定构造的布置和方法 金属元件的长度。

公开(公告)号：US06651013B1

公开(公告)日：2003-11-18

申请号：US09714372

申请日：2000-11-16

Applicant: How T. Lin ,  Christopher J. Majka ,  Matthew Francis Seward

Inventor： How T. Lin ,  Christopher J. Majka ,  Matthew Francis Seward

IPC: G01R3100

CPC classification number: G01R31/086

Abstract: A method and apparatus for locating a short between two nets in an electrical wire network of a microelectronic structure (e.g., chip, chip carrier, circuit card, etc.). A first net and a second net of the electrical wire are electrically shorted at an unknown point PS on the first net. Points PA and PB on the first net such are selected such that PS is located on a path between PA and PB along the first net. A constant current pulse source is electrically connected between PA and PB and is activated. Voltage drops VAB (from PA to PB) and VAC (from PA to a point PC on the second net) are measured. A length LAS of the path from PA to PS is calculated as a function of VAC/VAB. Computer graphics may be used to graphically display the location of the short within the microelectronic structure.

Abstract translation: 一种用于定位微电子结构（例如，芯片，芯片载体，电路卡等）的电线网络中的两个网之间的短路的方法和装置。 电线的第一网和第二网在第一网上的未知点PS处电短路。 选择第一网上的点PA和PB，使得PS位于沿着第一网的PA和PB之间的路径上。 恒流脉冲源电连接在PA和PB之间并被激活。 测量电压降VAB（从PA到PB）和VAC（从PA到第二网上的点PC）。 作为VAC / VAB的函数计算从PA到PS的路径的长度LAS。 计算机图形可用于在微电子结构内以图形方式显示短路的位置。

公开(公告)号：US06644864B2

公开(公告)日：2003-11-11

申请号：US10097767

申请日：2002-03-14

Applicant: Benson Chan ,  Richard R. Hall ,  How T. Lin ,  John H. Sherman

Inventor： Benson Chan ,  Richard R. Hall ,  How T. Lin ,  John H. Sherman

IPC: G02B638

CPC classification number: G02B6/3676 ,  G02B6/3636 ,  G02B6/3692 ,  G02B6/3885 ,  G02B6/4249

Abstract: The present invention relates generally to fiber optical arrays, and particularly, but not by way of limitation, to 3-dimentional array fiber optical couplers. More particularly, the present invention provides means of coupling semiconductor laser light sources to fiber-optic transmission devices.

Abstract translation: 本发明一般涉及光纤阵列，特别是涉及三维阵列光纤耦合器，而非限制性的。 更具体地，本发明提供了将半导体激光光源耦合到光纤传输装置的装置。

公开(公告)号：US08607445B1

公开(公告)日：2013-12-17

申请号：US13517776

申请日：2012-06-14

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin

IPC: H05K3/30

CPC classification number: H01G4/206 ,  H01G4/232 ,  H01G4/33 ,  H05K1/162 ,  H05K3/0032 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09881 ,  H05K2203/0108 ,  H05K2203/066

Abstract: A method of making a circuitized substrate which includes at least one and possibly several capacitors as part thereof. In one embodiment, the substrate is produced by forming a layer of capacitive dielectric material on a dielectric layer and thereafter forming channels with the capacitive material, e.g., using a laser. The channels are then filled with conductive material, e.g., copper, using selected deposition techniques, e.g., sputtering, electro-less plating and electroplating. A second dielectric layer is then formed atop the capacitor and a capacitor “core” results. This “core” may then be combined with other dielectric and conductive layers to form a larger, multilayered PCB or chip carrier. In an alternative approach, the capacitive dielectric material may be photo-imageable, with the channels being formed using conventional exposure and development processing known in the art.

Abstract translation: 一种制造电路化衬底的方法，其包括至少一个可能的几个电容器作为其一部分。 在一个实施例中，通过在电介质层上形成电容电介质材料层，然后用电容材料形成通道，例如使用激光来制造衬底。 然后使用所选择的沉积技术，例如溅射，无电镀和电镀，用导电材料（例如铜）填充通道。 然后在电容器顶部形成第二电介质层，并产生电容器“芯”。 然后，该“芯”可以与其它电介质层和导电层组合以形成较大的多层PCB或芯片载体。 在替代方法中，电容介电材料可以是可光成像的，其中通道是使用本领域已知的常规曝光和显影处理形成的。

公开(公告)号：US07897877B2

公开(公告)日：2011-03-01

申请号：US11438424

申请日：2006-05-23

Applicant: Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

Inventor： Rabindra N. Das ,  Frank D. Egitto ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L27/12 ,  H01L28/40 ,  H05K1/0306 ,  H05K3/125 ,  H05K3/4667 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2203/013

Abstract: A capacitive substrate and method of making same in which first and second glass layers are used. A first conductor is formed on a first of the glass layers and a capacitive dielectric material is positioned over the conductor. The second conductor is then positioned on the capacitive dielectric and the second glass layer positioned over the second conductor. Conductive thru-holes are formed to couple to the first and second conductors, respectively, such that the conductors and capacitive dielectric material form a capacitor when the capacitive substrate is in operation.

Abstract translation: 电容性基板及其制造方法，其中使用第一和第二玻璃层。 第一导体形成在第一玻璃层上，并且电容电介质材料位于导体上方。 然后将第二导体定位在电容电介质上，并且第二玻璃层位于第二导体上。 形成导电通孔以分别耦合到第一和第二导体，使得当电容基板工作时，导体和电容电介质材料形成电容器。

公开(公告)号：US07841741B2

公开(公告)日：2010-11-30

申请号：US11730404

申请日：2007-04-02

Applicant: Benson Chan ,  John E. Kozol ,  John M. Lauffer ,  How T. Lin

Inventor： Benson Chan ,  John E. Kozol ,  John M. Lauffer ,  How T. Lin

IPC: F21S4/00

CPC classification number: F21V29/70 ,  F21K9/00 ,  F21K9/69 ,  F21V29/85 ,  F21W2131/202 ,  F21W2131/205 ,  F21Y2115/10 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/10106

Abstract: An LED lighting assembly including a plurality of individual LEDs mounted on a common, bendable heat sinking member designed to remove heat from the LEDs during operation and also to be formed (bent) to provide the desired light direction and intensity. Several such assemblies may be used within an LED lamp, as also provided herein. The lamp is ideal for use within medical and dental environments to assure optimal light onto a patient located at a specified distance from the lamp.

Abstract translation: 一种LED照明组件，包括安装在公共的可弯曲的散热构件上的多个单独的LED，该散热构件被设计成在操作期间从LED移除热量并且还被形成（弯曲）以提供期望的光的方向和强度。 如本文也提供的，LED灯内可以使用若干这样的组件。 该灯是理想的在医疗和牙科环境中使用，以确保最佳的光照射到距离灯具指定距离的患者。

公开(公告)号：US07629559B2

公开(公告)日：2009-12-08

申请号：US11305073

申请日：2005-12-19

Applicant: Subahu D. Desai ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  Ronald V. Smith

Inventor： Subahu D. Desai ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  Ronald V. Smith

IPC: H05B1/02

CPC classification number: H05K3/4069 ,  H05K1/0293 ,  H05K3/105 ,  H05K2201/096 ,  H05K2203/105

Abstract: A method of improving conductive paste connections in a circuitized substrate in which at least one and preferably a series of high voltage pulses are applied across the paste and at least one and preferably a series of high current pulses are applied, both series of pulses applied separately. The result is an increase in the number of conductive paths through the paste connections from those present prior to the pulse applications and a corresponding resistance reduction in said connections.

Abstract translation: 一种改进电路化基板中的导电糊料连接的方法，其中施加至少一个并且优选一系列高压脉冲施加在该糊料上并且至少一个并且优选地一系列高电流脉冲，两个脉冲串分别施加 。 结果是通过粘合连接的导电路径的数量从在脉冲应用之前存在的导电路径的数量增加以及所述连接中相应的电阻减小。

公开(公告)号：US07541058B2

公开(公告)日：2009-06-02

申请号：US11907006

申请日：2007-10-09

Applicant: Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

Inventor： Benson Chan ,  How T. Lin ,  Roy H. Magnuson ,  Voya R. Markovich ,  Mark D. Poliks

IPC: G02B6/02 ,  H01L21/00 ,  G03G15/00 ,  G02B6/12

CPC classification number: G02B6/1221 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4246 ,  H05K1/0274

Abstract: A circuitized substrate (e.g., PCB) including an internal optical pathway as part thereof such that the substrate is capable of transmitting and/or receiving both electrical and optical signals. The substrate includes an angular reflector on one of the cladding layers such that optical signals passing through the optical core will impinge on the angled reflecting surfaces of the angular reflector and be reflected up through an opening (including one with optically transparent material therein), e.g., to a second circuitized substrate also having at least one internal optical pathway as part thereof, to thus interconnect the two substrates optically. A method of making the substrate is also provided.

公开(公告)号：US07441709B2

公开(公告)日：2008-10-28

申请号：US11086324

申请日：2005-03-23

Applicant: Benson Chan ,  How T. Lin ,  Voya R. Markovich ,  Ronald V. Smith

Inventor： Benson Chan ,  How T. Lin ,  Voya R. Markovich ,  Ronald V. Smith

IPC: G06K19/06

CPC classification number: G06K19/005 ,  G06K7/084 ,  G06K17/00 ,  G06K19/07354 ,  G06K2017/0064

Abstract: An electronic card assembly is provided which includes a protective housing having a movable card therein. The card, in one example one having a magnetic stripe, has its information erased when being inserted into the housing and re-written back onto its information portion (magnetic stripe) during card withdrawal, provided appropriate human information (e.g., from a fingerprint) is received by the assembly's reader component.

Abstract translation: 提供一种电子卡组件，其包括其中具有可移动卡的保护壳体。 在一个示例中具有磁条的卡在卡插入时被插入到壳体中被擦除并且在卡退出期间被重新写回到其信息部分（磁条）上，提供适当的人类信息（例如，从指纹） 被大会的阅读器组件接收。

公开(公告)号：US07152319B2

公开(公告)日：2006-12-26

申请号：US10811817

申请日：2004-03-30

Applicant: Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

Inventor： Benson Chan ,  John M. Lauffer ,  How T. Lin ,  Voya R. Markovich ,  David L. Thomas

IPC: H01K3/10

CPC classification number: H05K3/4688 ,  H01L23/3128 ,  H01L23/5383 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/024 ,  H05K1/113 ,  H05K3/4623 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2203/061 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2224/0401

Abstract: A multilayered PCB including two multilayered portions, one of these able to electrically connect electronic components mounted on the PCB to assure high frequency connections therebetween. The PCB further includes a conventional PCB portion to reduce costs while assuring a structure having a satisfactory overall thickness for use in the PCB field. Coupling is also possible to the internal portion from these components. Methods of making these structures have also been provided.

Abstract translation: 包括两个多层部分的多层PCB，其中之一能够电连接安装在PCB上的电子部件，以确保其间的高频连接。 PCB还包括常规PCB部分以降低成本，同时确保具有令人满意的整体厚度的结构以用于PCB领域。 这些组件的内部部分也可以进行耦合。 也提供了制造这些结构的方法。