公开(公告)号：US10529689B2

公开(公告)日：2020-01-07

申请号：US15660210

申请日：2017-07-26

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

公开(公告)号：US20180315718A1

公开(公告)日：2018-11-01

申请号：US16021383

申请日：2018-06-28

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/538 ,  H01L21/48

Abstract: Some embodiments of the present disclosure disclose a method for forming semiconductor packages. The method includes disposing a plurality of semiconductor chips over a top side of a wafer, molding the plurality of semiconductor chips with a first molding material, and after molding the semiconductor chips, forming a composite layer over the plurality of semiconductor chips.

公开(公告)号：US20180247906A1

公开(公告)日：2018-08-30

申请号：US15966447

申请日：2018-04-30

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05012 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/051 ,  H01L2224/05111 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05578 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/10125 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05341 ,  H01L2924/05432 ,  H01L2924/05442 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/01074

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US09922924B1

公开(公告)日：2018-03-20

申请号：US15369834

申请日：2016-12-05

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An interposer and a semiconductor package including the interposer are provided. The interposer includes a first dielectric layer, a conductive pillar, a conductive ring, a solder bump, and a redistribution layer. The first dielectric layer has an upper surface and a lower surface. The conductive pillar and the conductive ring are partially embedded in the first dielectric layer. A portion of the conductive pillar protrudes from the lower surface of the first dielectric layer. The conductive ring surrounds the conductive pillar, and a portion of the conductive ring protrudes from the lower surface of the first dielectric layer. The solder bump is disposed on the lower surface of the first dielectric layer, wherein the portion of the conductive pillar and the portion of the conductive ring are embedded in the solder bump. The redistribution layer is disposed on the upper surface of the first dielectric layer.

公开(公告)号：US09922845B1

公开(公告)日：2018-03-20

申请号：US15342124

申请日：2016-11-03

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L21/00 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/528 ,  H01L23/532 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A method for fabricating a semiconductor package is disclosed. A substrate is provided and a first passivation layer is formed on the substrate. Trenches are formed partially through the substrate. Metal via structures are formed in the trenches. An RDL structure is formed on the first passivation layer. A second passivation layer is formed on the RDL structure. Openings are formed in the second passivation layer to expose bump pads. First metal pillars are formed on the bump pads. Semiconductor dies are mounted onto the metal pillars. A molding compound is formed to cover the semiconductor dies. The substrate is removed, thereby exposing the first passivation layer and protrudent portions (second metal pillars) of the metal via structures. C4 bumps are formed directly on the second metal pillars, respectively.

公开(公告)号：US09916999B2

公开(公告)日：2018-03-13

申请号：US14731380

申请日：2015-06-04

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Hsu Chiang ,  Neng-Tai Shih

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/683 ,  H01L21/48 ,  H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/11312 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2221/68363 ,  H01L2924/00014

Abstract: A package structure and a method for fabricating thereof are provided. The package structure includes a substrate, a first connector, a redistribution layer, a second connector, and a chip. The first connector is disposed over the substrate. The redistribution layer is directly disposed over the first connector, and is connected to the substrate by the first connector. The redistribution layer includes a block layer, and a metal layer over the block layer. The second connector is directly disposed over the redistribution layer, and the chip is connected to the redistribution layer by the second connector.

公开(公告)号：US20170263469A1

公开(公告)日：2017-09-14

申请号：US15296058

申请日：2016-10-18

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L21/481 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5383 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/97 ,  H01L2924/1511 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1816 ,  H01L2924/18161 ,  H01L2924/182 ,  H01L2224/81

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side of the RDL interposer.

公开(公告)号：US09721923B1

公开(公告)日：2017-08-01

申请号：US15098341

申请日：2016-04-14

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/24137 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81

Abstract: A semiconductor package includes a first interposer, a second interposer, and a gap between the first interposer and the second interposer. The first interposer and the second interposer are coplanar. A first die is mounted on the first interposer and the second interposer. The first die includes first connection elements connecting the first die to the first interposer or the second interposer. A redistribution layer (RDL) structure is disposed on bottom surfaces of the first and second interposers for connecting the first interposer with the second interposer. The RDL structure includes at least one bridge trace traversing the gap to electrically connect the first interposer with the second interposer.

公开(公告)号：US20210202417A1

公开(公告)日：2021-07-01

申请号：US17198447

申请日：2021-03-11

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Tieh-Chiang Wu

IPC: H01L23/00

Abstract: A connector structure and a manufacturing method thereof are provided. The connector structure includes a semiconductor substrate, a metal layer, a passivation layer, and a conductive structure. The metal layer is over the semiconductor substrate. The passivation layer is over the metal layer and includes an opening. The conductive structure is in contact with the metal layer in a patterned surface structure of the conductive structure through the opening of the passivation layer.

公开(公告)号：US20210175188A1

公开(公告)日：2021-06-10

申请号：US17177431

申请日：2021-02-17

Applicant: Micron Technology, Inc.

Inventor： Shing-Yih Shih ,  Neng-Tai Shih

IPC: H01L23/00 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor device includes an interposer having a first side and a second side opposite to the first side, at least one active chip mounted on the first side within a chip mounting area through a plurality of first bumps, at least one dummy chip mounted on the first side within a peripheral area being adjacent to the chip mounting area, a molding compound disposed on the first side. The molding compound covers the at least one active chip and the at least one dummy chip. A plurality of solder bumps is mounted on the second side.