公开(公告)号：US11843055B2

公开(公告)日：2023-12-12

申请号：US16596339

申请日：2019-10-08

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Kirk D. Prall ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H10B12/00 ,  G11C11/409

CPC classification number: H01L29/78642 ,  G11C11/409 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/7869 ,  H10B12/05 ,  H10B12/30 ,  H10B12/50

Abstract: A transistor comprising threshold voltage control gates. The transistor also comprises active control gates adjacent opposing first sides of a channel region, the threshold voltage control gates adjacent opposing second sides of the channel region, and a dielectric region between the threshold voltage control gates and the channel region and between the active control gates and the channel region. A semiconductor device comprising memory cells comprising the transistor is also disclosed, as are systems comprising the memory cells, methods of forming the semiconductor device, and methods of operating a semiconductor device.

公开(公告)号：US20230327019A1

公开(公告)日：2023-10-12

申请号：US18207905

申请日：2023-06-09

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Ramaswamy Nirmal

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/516 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/785 ,  H01L29/66522 ,  H01L29/6684

Abstract: Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

公开(公告)号：US11778824B2

公开(公告)日：2023-10-03

申请号：US17140494

申请日：2021-01-04

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Mojtaba Asadirad

IPC: H10B43/27 ,  H01L29/10 ,  H01L23/522 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/14

CPC classification number: H10B43/27 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/53271 ,  H01L29/1037 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/0262 ,  H01L21/02546

Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

公开(公告)号：US11778806B2

公开(公告)日：2023-10-03

申请号：US17388678

申请日：2021-07-29

Applicant: Micron Technology, Inc.

Inventor： Eric S. Carman ,  Durai Vishak Nirmal Ramaswamy ,  Richard E Fackenthal ,  Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Duane R. Mills ,  Christian Caillat

IPC: G11C11/34 ,  H10B12/00 ,  H01L29/24 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4094 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B12/20 ,  G11C11/4074 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  H01L29/24 ,  H10B12/50 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

公开(公告)号：US11776907B2

公开(公告)日：2023-10-03

申请号：US17003065

申请日：2020-08-26

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

IPC: H01L23/528 ,  H01L29/24 ,  G11C5/06 ,  H10B12/00

CPC classification number: H01L23/5286 ,  G11C5/063 ,  H01L29/24 ,  H10B12/01 ,  H10B12/20

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a data line, a memory cell coupled to the data line, a ground connection, and a conductive line. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the data line, and a charge storage structure electrically separated from the first region. The second transistor includes a second region electrically coupled to the charge storage structure and the data line. The ground connection is coupled to the first region of the first transistor. The conductive line is electrically separated from the first and second regions and spans across part of the first region of the first transistor and part of the second region of the second transistor and forming a gate of the first and second transistors.

公开(公告)号：US11770932B2

公开(公告)日：2023-09-26

申请号：US18045417

申请日：2022-10-10

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kunal R. Parekh

IPC: H01L21/00 ,  H10B43/27 ,  H01L29/47 ,  H01L21/285 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L21/28537 ,  H01L29/47 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A microelectronic device comprises a stack structure, cell pillar structures, an active body structure, digit line structures, and control logic devices. The stack structure comprises vertically neighboring tiers, each of the vertically neighboring tiers comprising a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structures vertically extend through the stack structure and each comprise a channel material and an outer material stack horizontally interposed between the channel material and the stack structure. The active body structure vertically overlies the stack structure and is in contact with the channel material of the cell pillar structures. The active body structure comprises a metal material having a work function greater than or equal to about 4.7 electronvolts. The digit line structures vertically underlie the stack structure and are coupled to the cell pillar structures. Memory devices, electronic systems, and methods of forming a microelectronic device are also described.

公开(公告)号：US11727983B2

公开(公告)日：2023-08-15

申请号：US17353090

申请日：2021-06-21

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy

IPC: G11C11/4096 ,  G11C11/4094 ,  H10B12/00

CPC classification number: G11C11/4096 ,  G11C11/4094 ,  H10B12/50

Abstract: Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes multiple two-transistor (2T) memory cells. Each of the multiple 2T memory cells includes: a p-channel field effect transistor (PFET) including a charge storage node and a read channel portion, an n-channel field effect transistor (NFET) including a write channel portion that is directly coupled to the charge storage node of the PFET; a single bit line pair coupled to the read channel portion of the PFET; and a single access line overlapping at least part of each of the read channel portion and the write channel portion.

公开(公告)号：US20230240077A1

公开(公告)日：2023-07-27

申请号：US18126679

申请日：2023-03-27

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Eric S. Carman ,  Karthik Sarpatwari ,  Durai Vishak Nirmal Ramaswamy ,  Richard E. Fackenthal ,  Haitao Liu

IPC: H10B43/50 ,  H01L29/423 ,  H01L29/10

CPC classification number: H10B43/50 ,  H01L29/1062 ,  H01L29/42396

Abstract: Some embodiments include apparatuses and methods forming the apparatuses. One of the apparatuses includes a first transistor including a first channel region, and a charge storage structure separated from the first channel region; a second transistor including a second channel region formed over the charge storage structure; and a data line formed over and contacting the first channel region and the second channel region, the data line including a portion adjacent the first channel region and separated from the first channel region by a dielectric material.

公开(公告)号：US11706929B2

公开(公告)日：2023-07-18

申请号：US17561579

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Qian Tao ,  Durai Vishak Nirmal Ramaswamy ,  Haitao Liu ,  Kirk D. Prall ,  Ashonita Chavan

IPC: H01L27/08 ,  H01L49/02 ,  H10B53/00 ,  H01G4/33 ,  H01G4/40 ,  H01G4/008 ,  H10B12/00 ,  H10B53/30 ,  H01G4/08

CPC classification number: H10B53/00 ,  H01G4/008 ,  H01G4/08 ,  H01G4/33 ,  H01G4/40 ,  H01L28/40 ,  H01L28/75 ,  H10B12/033 ,  H10B53/30 ,  H10B12/30

Abstract: A memory cell includes a select device and a capacitor electrically coupled in series with the select device. The capacitor includes two conductive capacitor electrodes having ferroelectric material there-between. The capacitor has an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material. There is a parallel current leakage path from the one capacitor electrode to the other. The parallel current leakage path is circuit-parallel the intrinsic path and of lower total resistance than the intrinsic path. Other aspects are disclosed.

公开(公告)号：US20230223434A1

公开(公告)日：2023-07-13

申请号：US17647912

申请日：2022-01-13

Applicant: Micron Technology, Inc.

Inventor： Gaurav Musalgaonkar ,  Naveen Kaushik ,  Sonam Jain ,  Haitao Liu ,  Chittoor Ranganathan Parthasarathy

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0626 ,  H01L27/088 ,  H01L29/7816 ,  H01L29/66681

Abstract: An apparatus includes lightly doped drain regions vertically extending into a semiconductor substrate. A channel region is horizontally interposed between the lightly doped drain regions, and source/drain regions vertically extend into the lightly doped drain regions. Breakdown-enhancement implant intrusion regions are within the lightly doped drain regions and are horizontally interposed between the channel region and the source/drain regions. The breakdown enhancement implant regions have a different chemical species than the lightly doped drain regions and have upper boundaries vertically underlying upper boundaries of the lightly doped drain regions. The apparatus also has a gate structure vertically overlying the channel regions and it is horizontally interposed between the breakdown-enhancement implant regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.