公开(公告)号：US20160035891A1

公开(公告)日：2016-02-04

申请号：US14448548

申请日：2014-07-31

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Kern RIM ,  Stanley Seungchul SONG ,  Choh Fei YEAP

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L29/49 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/785

Abstract: A fin field-effect transistor (FinFET) includes a gate stack on a surface of a semiconductor fin. The semiconductor fin may include a capping material and a stressor material. The stressor material is confined by the capping material to a region proximate the gate stack. The stressor material provides stress on the semiconductor fin proximate the gate stack.

Abstract translation: 鳍状场效应晶体管（FinFET）包括在半导体鳍片的表面上的栅极堆叠。 半导体鳍片可以包括封盖材料和应力源材料。 应力源材料被封盖材料限制在靠近栅极叠层的区域。 应力源材料在靠近栅极堆叠的半导体鳍片上提供应力。

公开(公告)号：US20180166340A1

公开(公告)日：2018-06-14

申请号：US15880512

申请日：2018-01-25

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/51 ,  H01L27/088 ,  H01L29/161 ,  H01L29/49

CPC classification number: H01L21/82345 ,  H01L21/02244 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/4966 ,  H01L29/517

Abstract: A first and a second instance of a common structured stack are formed, respectively, on a first fin and a second fin. The common structured stack includes a work-function metal layer, and a barrier layer. The barrier layer of the first instance of the common structured stack is etched through, and the work-function metal layer of the first instance of the common structure is partially etched. The partial etch forms a thinner work-function metal layer, having an oxide of the work-function metal as a new barrier layer. A gate element is formed on the new barrier layer.

公开(公告)号：US20160155748A1

公开(公告)日：2016-06-02

申请号：US14556983

申请日：2014-12-01

Applicant: QUALCOMM Incorporated

Inventor： Xia LI ,  Jeffrey Junhao XU ,  Zhongze WANG ,  Bin YANG ,  Xiaonan CHEN ,  Yu LU

IPC: H01L27/115 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02 ,  H01L29/788 ,  H01L29/51

CPC classification number: H01L21/28088 ,  G11C16/0408 ,  H01L21/02148 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/7883

Abstract: Non-volatile memory devices and logic devices are fabricated using processes compatible with high dielectric constant/metal gate (HK/MG) processes for increased cell density and larger scale integration. A doped oxide layer, such as a silicon-doped hafnium oxide (HfO2) layer, is implemented as a ferroelectric dipole layer in a non-volatile memory device

Abstract translation: 使用与高介电常数/金属栅（HK / MG）工艺兼容的工艺制造非易失性存储器件和逻辑器件，用于增加电池密度和更大规模的集成。 掺杂氧化物层，例如掺杂硅的氧化铪（HfO 2）层，被实现为非易失性存储器件中的铁电偶极子层

公开(公告)号：US20160013133A1

公开(公告)日：2016-01-14

申请号：US14330950

申请日：2014-07-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Matthew Michael NOWAK ,  Jeffrey Junhao XU

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76895 ,  H01L21/7682 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/53257 ,  H01L23/53295 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Systems and methods are directed to a semiconductor device, which includes an integrated circuit, wherein the integrated circuit includes at least a first layer comprising two or more Tungsten lines and at least one air gap between at least two Tungsten lines, the air gaps to reduce capacitance. An interposer is coupled to the integrated circuit, to reduce stress on the two or more Tungsten lines and the at least one air gap. A laminated package substrate may be attached to the interposer such that the interposer is configured to absorb mechanical stress induced by mismatch in coefficient of thermal expansion (CTE) between the laminated package substrate and the interposer and protect the air gap from the mechanical stress.

Abstract translation: 系统和方法涉及包括集成电路的半导体器件，其中集成电路至少包括包含两条或更多条钨线的至少一条第一层和至少两条钨线之间的至少一个气隙，所述气隙减少 电容。 插入器耦合到集成电路，以减少两个或多个钨线和至少一个气隙的应力。 层叠封装基板可以附接到插入件，使得插入件被构造成吸收由层压封装基板和插入件之间的热膨胀系数（CTE）失配引起的机械应力，并保护气隙免受机械应力。

公开(公告)号：US20150249038A1

公开(公告)日：2015-09-03

申请号：US14274099

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  John Jianhong ZHU ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

Abstract translation: 半导体器件包括具有将第一互连层耦合到沟槽的通孔的管芯。 半导体器件还包括在沟槽的侧壁和相邻表面上以及在通孔的侧壁上的阻挡层。 半导体器件在第一互连层的表面上具有掺杂的导电层。 掺杂导电层在通孔的侧壁之间延伸。 半导体器件还包括在通孔和沟槽中的阻挡层上的导电材料。 导电材料位于设置在第一互连层表面上的掺杂导电层上。

公开(公告)号：US20150145069A1

公开(公告)日：2015-05-28

申请号：US14269828

申请日：2014-05-05

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L21/324 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/66803 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.

Abstract translation: 在翅片场效应晶体管（FinFET）中制造鳍片的方法包括曝光耦合到FinFET衬底的单晶鳍结构。 单晶鳍结构是第一种材料。 该方法还包括在第一温度下将第二材料注入到暴露的单晶鳍结构中。 第一个温度降低了单晶翅片结构的非晶化。 植入的单晶鳍结构包括至少20％的第一材料。 该方法还包括在第二温度下退火植入的翅片结构。 第二温度降低植入翅片结构中的晶体缺陷以形成翅片。

公开(公告)号：US20170077090A1

公开(公告)日：2017-03-16

申请号：US14852954

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Stanley Seungchul SONG ,  Kern RIM ,  Jeffrey Junhao XU ,  John Jianhong ZHU ,  Jun CHEN ,  Da YANG ,  Choh Fei YEAP

IPC: H01L27/088 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/76897 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/0696 ,  H01L29/66545

Abstract: A multi-cell transistor includes gate body elements, gate tip elements extending from the gate body elements, and gate extensions extending from the gate tip elements. A patterned metal layer is provided between adjacent gate elements and at least portions of adjacent gate tip elements. Spacers are provided on the sides of each gate body element and each gate tip element to prevent the patterned metal layer from creating a short circuit between adjacent gate tip elements.

Abstract translation: 多单元晶体管包括门体元件，从栅极体元件延伸的栅极尖端元件以及从栅极尖端元件延伸的栅极延伸。 在相邻的栅极元件和相邻栅极尖端元件的至少一部分之间提供图案化的金属层。 隔板设置在每个门体元件和每个门尖元件的侧面上，以防止图案化的金属层在相邻的门尖元件之间产生短路。

公开(公告)号：US20160351677A1

公开(公告)日：2016-12-01

申请号：US14723199

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Junjing BAO ,  Haining YANG ,  Yanxiang LIU ,  Jeffrey Junhao XU

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/311 ,  H01L29/40 ,  H01L27/088 ,  H01L21/3105 ,  H01L21/3213 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/288

CPC classification number: H01L29/495 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

Abstract: A sacrificial cap is grown on an upper surface of a conductor. A dielectric spacer is against a side of the conductor. An upper dielectric side spacer is formed on a sidewall of the sacrificial cap. The sacrificial cap is selectively etched, leaving a cap recess, and the upper dielectric side spacer facing the cap recess. Silicon nitride is filled in the cap recess, to form a center cap and a protective cap having center cap and the upper dielectric spacer.

Abstract translation: 在导体的上表面上生长牺牲帽。 电介质隔离物抵靠导体的一侧。 在绝缘帽的侧壁上形成上绝缘侧绝缘体。 选择性地蚀刻牺牲帽，留下盖子凹槽，并且上电介质侧隔片面向盖凹槽。 氮化硅填充在盖凹部中，以形成中心帽和具有中心盖和上部电介质间隔物的保护帽。

公开(公告)号：US20160233126A1

公开(公告)日：2016-08-11

申请号：US15133040

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  John Jianhong ZHU ,  Choh Fei YEAP

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76843 ,  H01L21/76831 ,  H01L21/76847 ,  H01L21/76855 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76864 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a die having a via coupling a first interconnect layer to a trench. The semiconductor device also includes a barrier layer on sidewalls and adjacent surfaces of the trench, and on sidewalls of the via. The semiconductor device has a doped conductive layer on a surface of the first interconnect layer. The doped conductive layer extends between the sidewalls of the via. The semiconductor device further includes a conductive material on the barrier layer in both the via and the trench. The conductive material is on the doped conductive layer disposed on the surface of the first interconnect layer.

公开(公告)号：US20160225881A1

公开(公告)日：2016-08-04

申请号：US15097127

申请日：2016-04-12

Applicant: QUALCOMM Incorporated

Inventor： Jeffrey Junhao XU ,  Choh Fei YEAP

IPC: H01L29/66 ,  H01L21/324 ,  H01L29/06 ,  H01L21/265 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L29/66803 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/0603 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/785

Abstract: Methods for fabricating a fin in a fin field effect transistor (FinFET), include exposing a single crystal fin structure coupled to a substrate of the FinFET. The single crystal fin structure is of a first material. The method further includes implanting a second material into the exposed single crystal fin structure at a first temperature. The first temperature reduces amorphization of the single crystal fin structure. The implanted single crystal fin structure comprises at least 20% of the first material. The method also includes annealing the implanted fin structure at a second temperature. The second temperature reduces crystal defects in the implanted fin structure to form the fin.