公开(公告)号：US20170005160A1

公开(公告)日：2017-01-05

申请号：US14973479

申请日：2015-12-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Yue LI ,  Ratibor RADOJCIC

IPC: H01L49/02 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/53228 ,  H01L28/75

Abstract: Copper (Cu) grain boundaries can move during a thermal cycle resulting in the Cu grain position being offset. Such Cu pumping can disturb the surface of a bottom metal, and can physically break a dielectric of a metal-insulator-metal (MIM) capacitor. By capping the bottom metal with an anchoring cap, Cu pumping is reduced or eliminated.

Abstract translation: 铜（Cu）晶界可以在热循环期间移动，导致Cu晶粒位置偏移。 这种Cu泵浦可能会干扰底部金属的表面，并且可以物理地破坏金属 - 绝缘体 - 金属（MIM）电容器的电介质。 通过用锚固帽盖住底部金属，减少或消除Cu泵送。

公开(公告)号：US20160093591A1

公开(公告)日：2016-03-31

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  Wenyue ZHANG ,  Yang DU ,  Yong Ju LEE ,  Shiqun GU ,  Jing XIE

IPC: H01L25/065 ,  H01L27/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/683 ,  H01L21/265 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

Abstract translation: 提供了用于制造具有两层或多层的三维集成电路（3D IC）装置的微机电系统（MEMS）键释放结构。 MEMS键释放结构包括可以具有柱或柱结构的MEMS牺牲脱离层，或者替代地，用于粘合和释放的连续牺牲层。

公开(公告)号：US20160043068A1

公开(公告)日：2016-02-11

申请号：US14454851

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Shiqun GU

IPC: H01L27/02 ,  H01L21/48 ,  H01L23/498 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0255 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated interposer includes an interposer substrate including at least a first portion of a 3D passive device within an active region of the interposer substrate. The integrated interposer also includes an inter-conductive dielectric layer on an active surface of the active region of the interposer substrate, the inter-conductive dielectric layer including at least a second portion of the 3D passive device. The integrated interposer further includes a contact layer coupled to the 3D passive devices and configured to couple at least one die to the integrated interposer. The integrated interposer also includes at least one through via coupled to the contact layer and extending through the interposer substrate to a passive surface of the interposer substrate. The integrated interposer further includes an interconnect layer on the passive surface of the interposer substrate and coupled to the at least one through via.

Abstract translation: 集成插入器包括插入器基板，其包括在内插器基板的有源区域内的3D无源器件的至少第一部分。 该集成插入器还包括在该插入器基板的有源区域的有源表面上的导电介电层，该导电介质层至少包括该3D无源器件的第二部分。 集成中介层还包括耦合到3D无源器件并被配置为将至少一个管芯耦合到集成插入器的接触层。 集成插入器还包括至少一个通孔，其连接到接触层并且延伸穿过插入器衬底到内插器衬底的无源表面。 集成插入器还包括在插入器基板的被动表面上并且耦合到至少一个通孔的互连层。

公开(公告)号：US20180083588A1

公开(公告)日：2018-03-22

申请号：US15350969

申请日：2016-11-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Shiqun GU ,  Je-Hsiung Jeffrey LAN ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Chengjie ZUO

IPC: H03H1/00 ,  H01G4/12 ,  H01G4/005 ,  H01G4/40 ,  H03H7/46

CPC classification number: H03H1/00 ,  H01G4/005 ,  H01G4/012 ,  H01G4/1209 ,  H01G4/33 ,  H01G4/40 ,  H01L23/5223 ,  H01L28/60 ,  H03H7/46 ,  H03H7/463 ,  H03H2001/0014 ,  H03H2001/0021 ,  H04B1/0057 ,  H04B1/0458 ,  H04B1/18

Abstract: A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.

公开(公告)号：US20170373175A1

公开(公告)日：2017-12-28

申请号：US15192773

申请日：2016-06-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Gengming TAI ,  Je-Hsiung LAN ,  Matthew Michael NOWAK ,  Miguel MIRANDA CORBALAN ,  Steve FANELLI

IPC: H01L29/737 ,  H01L23/31 ,  H01L29/08 ,  H01L29/66

Abstract: Disclosed is a heterojunction bipolar transistor, and method of manufacturing the same, including an emitter having a conductive emitter contact coupled to a first side of the emitter, a first side of a base coupled to a second side of the emitter opposite the first side of the emitter, a collector coupled to the base on a second side of the base opposite the emitter, wherein an area of a junction between the base and the collector is less than or equal to an area of a junction between the base and the emitter, a first conductive base contact coupled to the base, and a conductive collector contact coupled to the collector on the side of the collector opposite the emitter and substantially parallel to the first conductive base contact.

公开(公告)号：US20170360316A1

公开(公告)日：2017-12-21

申请号：US15186347

申请日：2016-06-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Matthew Michael NOWAK ,  Kenneth KASKOUN ,  Eugene DANTSKER ,  Russel Allyn MARTIN

IPC: A61B5/024 ,  A61B5/1455 ,  A61B5/145 ,  A61B5/00

CPC classification number: A61B5/02433 ,  A61B5/14532 ,  A61B5/14551 ,  A61B5/14552 ,  A61B5/681 ,  A61B5/6823 ,  A61B5/6824 ,  A61B5/6828 ,  A61B5/7278 ,  A61B5/742 ,  A61B5/7475 ,  A61B2560/0214 ,  A61B2560/0475 ,  A61B2562/04 ,  A61B2562/046 ,  A61B2562/164

Abstract: Examples of monolithic integrated emitter-detector array in a flexible substrate for biometric sensing and associated devices and methods are disclosed. One disclosed example device includes a flexible substrate; a first array of emitters embedded in the flexible substrate, the first array of emitters configured to emit first electromagnetic (EM) signals; a first array of detectors embedded in the flexible substrate, the first array of detectors configured to detect reflections of the first EM signals; a first scanning circuit coupled to the first array of emitters, the first scanning circuit configured to selectively activate individual emitters of the first array of emitters; and a first sensing circuit coupled to individual detectors of the first array of detectors, the first sensing circuit configured to receive a detection signal from at least one of the detectors of the first array of detectors.

公开(公告)号：US20140302674A1

公开(公告)日：2014-10-09

申请号：US14311405

申请日：2014-06-23

Applicant: QUALCOMM Incorporated

Inventor： Vidhya RAMACHANDRAN ,  Shiqun GU

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.

Abstract translation: 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 用于TSV应变消除的方法包括在衬底中限定通孔的通孔。 该方法还包括在空腔中沉积隔离层。 该方法还包括用导电材料填充空腔。 该方法还包括去除隔离层的一部分以形成凹陷部分。

公开(公告)号：US20190081607A1

公开(公告)日：2019-03-14

申请号：US15705035

申请日：2017-09-14

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Jonghae KIM ,  Changhan Hobie YUN ,  David Francis BERDY ,  Shiqun GU ,  Chengjie ZUO

IPC: H03H7/01 ,  H01L49/02 ,  H01L23/532 ,  H03H3/00 ,  H01L27/01 ,  H01L23/522 ,  H01L23/528

Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.

公开(公告)号：US20180233604A1

公开(公告)日：2018-08-16

申请号：US15431623

申请日：2017-02-13

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Gengming TAO ,  Richard HAMMOND ,  Ranadeep DUTTA ,  Matthew Michael NOWAK ,  Francesco CAROBOLANTE

IPC: H01L29/93 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/737 ,  H01L29/66 ,  H01L27/06 ,  H01L21/822 ,  H01L23/00 ,  H01L23/66 ,  H03H11/34 ,  H03H11/04

CPC classification number: H01L29/93 ,  H01L21/8221 ,  H01L23/66 ,  H01L24/13 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/20 ,  H01L29/22 ,  H01L29/47 ,  H01L29/66174 ,  H01L29/66242 ,  H01L29/7371 ,  H01L2224/13025 ,  H03H11/04 ,  H03H11/342

Abstract: A tunable capacitor may include a first terminal having a first semiconductor component with a first polarity. The tunable capacitor may also include a second terminal having a second semiconductor component with a second polarity. The second component may be adjacent to the first semiconductor component. The tunable capacitor may further include a first conductive material electrically coupled to a first depletion region at a first sidewall of the first semiconductor component.

公开(公告)号：US20180167054A1

公开(公告)日：2018-06-14

申请号：US15379392

申请日：2016-12-14

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Changhan Hobie YUN ,  Shiqun GU ,  Niranjan Sunil MUDAKATTE ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H03H9/64 ,  H03H3/08 ,  H03H9/72

CPC classification number: H03H9/64 ,  H03H3/08 ,  H03H9/0523 ,  H03H9/0547 ,  H03H9/0561 ,  H03H9/059 ,  H03H9/72

Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.