公开(公告)号：US08980689B2

公开(公告)日：2015-03-17

申请号：US14088576

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoung-Soo Kwak ,  Cha-Jea Jo ,  Tae-Je Cho ,  Sang-Uk Han

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L25/00

CPC classification number: H01L25/50 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a method of fabricating a multi-chip stack package. The method includes preparing single-bodied lower chips having a single-bodied lower chip substrate having a first surface and a second surface disposed opposite the first surface, bonding unit package substrates onto the first surface of the single-bodied lower chip substrate to form a single-bodied substrate-chip bonding structure, separating the single-bodied substrate-chip bonding structure into a plurality of unit substrate-chip bonding structures, preparing single-bodied upper chips having a single-bodied upper chip substrate, bonding the plurality of unit substrate-chip bonding structures onto a first surface of the single-bodied upper chip substrate to form a single-bodied semiconductor chip stack structure, and separating the single-bodied semiconductor chip stack structure into a plurality of unit semiconductor chip stack structures.

Abstract translation: 提供一种制造多芯片堆叠封装的方法。 该方法包括制备具有单体下部芯片衬底的单体下部芯片，其具有第一表面和与第一表面相对设置的第二表面，将单元封装衬底粘合到单体下部芯片衬底的第一表面上以形成 单体衬底芯片接合结构，将单体衬底 - 芯片接合结构分离成多个单元衬底 - 芯片接合结构，制备具有单体上片状衬底的单体上片，将多个单元 衬底 - 芯片接合结构到单体上芯片衬底的第一表面上以形成单体半导体芯片堆叠结构，并将单体半导体芯片堆叠结构分离成多个单元半导体芯片堆栈结构。

公开(公告)号：US11830803B2

公开(公告)日：2023-11-28

申请号：US17699525

申请日：2022-03-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwanjai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/4985 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/73 ,  H01L2224/73204

Abstract: A chip-on-film package may include a film substrate including a chip region and an edge region, a semiconductor chip provided on the chip region and mounted on a top surface of the film substrate, the semiconductor chip including a chip pad adjacent to a bottom surface thereof, an input line and an output line provided on the edge region and disposed on the top surface of the film substrate, a connection terminal interposed between the film substrate and the semiconductor chip, and a redistribution pattern disposed between the semiconductor chip and the connection terminal.

公开(公告)号：US11710757B2

公开(公告)日：2023-07-25

申请号：US17227650

申请日：2021-04-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ohguk Kwon ,  Hyoeun Kim ,  Sunkyoung Seo ,  Sang-Uk Han

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L27/14634 ,  H01L23/481 ,  H01L24/08 ,  H01L24/73 ,  H01L24/89 ,  H01L27/1469 ,  H01L27/14627 ,  H01L2224/08146 ,  H01L2224/73204 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a molding layer, a silicon layer on the molding layer, a glass upwardly spaced apart from the silicon layer, and a connection dam coupled to the silicon layer and connecting the silicon layer to the glass. The silicon layer includes a silicon layer body, a silicon layer via extending vertically in the silicon layer body, and a micro-lens array on a top surface of the silicon layer body. A bottom surface of the silicon layer body contacts a top surface of the molding layer. The molding layer includes a molding layer body, a molding layer via that extends vertically in the molding layer body and has electrical connection with the silicon layer via, and a connection ball connected to a bottom surface of the molding layer via.

公开(公告)号：US11600556B2

公开(公告)日：2023-03-07

申请号：US17230662

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minki Kim ,  Duckgyu Kim ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367

Abstract: Disclosed is a semiconductor package comprising a semiconductor chip, a first chip pad on a bottom surface of the semiconductor chip and adjacent to a first lateral surface in a first direction of the semiconductor chip, the first lateral surface separated from the first chip pad from a plan view in a first direction, and a first lead frame coupled to the first chip pad. The first lead frame includes a first segment on a bottom surface of the first chip pad and extending from the first chip pad in a second direction opposite to the first direction and away from the first lateral surface of the semiconductor chip, and a second segment which connects to a first end of the first segment and then extends along the first direction to extend beyond the first lateral surface of the semiconductor chip after passing one side of the first chip pad, when viewed in the plan view.

公开(公告)号：US11158603B2

公开(公告)日：2021-10-26

申请号：US16298476

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Ji Hwang Kim ,  Jisun Yang ,  Seunghoon Yeon ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

公开(公告)号：US10978431B2

公开(公告)日：2021-04-13

申请号：US16287249

申请日：2019-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361170B2

公开(公告)日：2019-07-23

申请号：US15837187

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Pyo ,  Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US09241407B2

公开(公告)日：2016-01-19

申请号：US13747832

申请日：2013-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jeong-Kyu Ha ,  Youngshin Kwon ,  KwanJai Lee ,  Jae-Min Jung ,  KyongSoon Cho ,  Sang-Uk Han

IPC: H01L23/14 ,  H05K1/11 ,  H05K3/10 ,  H01L23/00 ,  H05K3/00 ,  H05K1/18 ,  H05K3/42

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/78 ,  H01L23/145 ,  H01L23/49524 ,  H01L23/49827 ,  H01L23/4985 ,  H01L24/50 ,  H01L2924/12042 ,  H05K1/114 ,  H05K1/115 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/107 ,  H05K3/42 ,  H05K2203/1545 ,  Y10T156/1052 ,  H01L2924/00

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract translation: 提供包括绝缘图案的胶带包装; 绝缘图案中的通孔中的通孔接触; 从所述通孔接触延伸到所述绝缘图案的切割表面的第一互连图案; 以及连接到绝缘图案下方的通孔接点的第二互连图案。 第二互连图案平行于第一互连图案并与绝缘图案的切割表面间隔开。

公开(公告)号：US20140299980A1

公开(公告)日：2014-10-09

申请号：US14160008

申请日：2014-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun-Kyoung Choi ,  Jong-Youn Kim ,  Sang-Wook Park ,  Hae-Jung Yu ,  In-Young Lee ,  Sang-Uk Han ,  Ji-Seok Hong

IPC: H01L23/522 ,  H01L23/34

CPC classification number: H01L24/97 ,  H01L21/561 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract translation: 提供了包括散热器的半导体封装及其形成方法。 半导体封装可以包括顺序堆叠的第一半导体芯片，第二半导体芯片和散热器。 半导体封装还可以包括围绕第二半导体芯片并直接接触第二半导体芯片的侧壁的热界面材料（TIM）层。 TIM层的上表面可以直接接触散热器的下表面，并且TIM层的侧壁可以与散热器的侧壁基本上共面。 在一些实施例中，第一半导体芯片的侧壁可以与TIM层的侧壁基本共面。

公开(公告)号：US20130240917A1

公开(公告)日：2013-09-19

申请号：US13780648

申请日：2013-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyong soon Cho ,  KwanJai Lee ,  Jae-Min Jung ,  Jeong-Kyu Ha ,  Sang-Uk Han

IPC: H01L23/525 ,  H02H9/04

CPC classification number: H01L23/5256 ,  H01L23/4985 ,  H01L23/60 ,  H01L2924/0002 ,  H02H9/041 ,  H01L2924/00

Abstract: A semiconductor package is provided. The semiconductor package may include a base film having a first surface and a second surface opposite the first surface, an interconnection pattern on the first surface of the base film, and a ground layer on the second surface of the base film. The semiconductor package may further include a semiconductor chip on the first surface of the base film within the first region and a via contact plug in the second region that penetrates the base film and is configured to electrically connect the interconnection pattern with the ground layer when electrostatic discharge occurs through the via contact plug.

Abstract translation: 提供半导体封装。 半导体封装可以包括具有第一表面和与第一表面相对的第二表面的基膜，在基膜的第一表面上的互连图案和基膜的第二表面上的接地层。 所述半导体封装还可以包括在所述第一区域内的所述基膜的第一表面上的半导体芯片和穿过所述基膜的所述第二区域中的通孔接触插塞，并且被配置为当静电时将所述互连图案与所述接地层电连接 通过通孔接触插头发生放电。