公开(公告)号：US20160322969A1

公开(公告)日：2016-11-03

申请号：US15133644

申请日：2016-04-20

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji PADMANABHAN ,  Prasad VENKATRAMAN ,  Peter MOENS ,  Mihir MUDHOLKAR ,  Joe FULTON ,  Philip CELAYA ,  Stephen ST. GERMAIN ,  Chun-Li LIU ,  Jason MCDONALD ,  Alexander YOUNG ,  Ali SALIH

IPC: H03K17/687 ,  H01L25/11 ,  H01L29/778

CPC classification number: H01L29/747 ,  H01L21/8258 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/40 ,  H01L25/115 ,  H01L25/18 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/0883 ,  H01L29/205 ,  H01L29/404 ,  H01L29/4238 ,  H01L29/7416 ,  H01L29/742 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2924/00014 ,  H03K17/6874 ,  H03K2017/6878 ,  H03K2217/0009 ,  H03K2217/0018 ,  H01L2224/37099

Abstract: A half-bridge circuit can include a high-side HEMT, a high-side switch transistor, a low-side HEMT, and a low-side switch transistor. The die substrates of the HEMTs can be coupled to the sources of their corresponding switch transistors. In another aspect, a packaged electronic device for a half-bridge circuit can have a design that can use shorter connectors that help to reduce parasitic inductance and resistance. In a further aspect, a packaged electronic device for a half-bridge circuit can include more than one connection along the bottom of the package allows less lead connections along the periphery of the packaged electronic device and can allow for a smaller package.

Abstract translation: 半桥电路可以包括高侧HEMT，高侧开关晶体管，低侧HEMT和低侧开关晶体管。 HEMT的管芯衬底可以耦合到其相应的开关晶体管的源极。 在另一方面，用于半桥电路的封装电子器件可以具有可以使用有助于减小寄生电感和电阻的较短连接器的设计。 在另一方面，用于半桥电路的封装电子设备可以包括沿着封装底部的多于一个的连接允许沿着封装的电子器件的周边的较少的引线连接并且可以允许较小的封装。

公开(公告)号：US20160276250A1

公开(公告)日：2016-09-22

申请号：US15166065

申请日：2016-05-26

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Stephen ST. GERMAIN ,  Roger ARBUTHNOT ,  Peter MOENS

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/31 ,  H01L29/20

CPC classification number: H01L23/49524 ,  H01L21/4825 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/482 ,  H01L23/4824 ,  H01L23/49562 ,  H01L24/16 ,  H01L24/83 ,  H01L29/0696 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/78 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16245 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A semiconductor package. Implementations may include a lateral device that may include a lateral semiconductor device including one of interspersed and interdigitated source and drain regions and one or more gate regions, a single layer clip, and a leadframe. The single layer clip may be coupled to the one of interspersed and interdigitated source and drain regions and the one or more gate regions and to the leadframe. The single layer clip may be configured to redistribute and to isolate source, drain, and gate signals passing into and out from the lateral semiconductor device during operation of the semiconductor device package.

Abstract translation: 半导体封装。 实施方案可以包括横向设备，其可以包括横向半导体器件，其包括散在和交叉的源极和漏极区域之一以及一个或多个栅极区域，单层夹子和引线框架。 单层夹可以耦合到散在和交叉的源极和漏极区域以及一个或多个栅极区域和引线框架中的一个。 单层夹可以被配置为在半导体器件封装的操作期间重新分布并隔离通过和流出半导体器件的源极，漏极和栅极信号。

公开(公告)号：US20240290758A1

公开(公告)日：2024-08-29

申请号：US18398499

申请日：2023-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L23/367 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32245

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

公开(公告)号：US20240203846A1

公开(公告)日：2024-06-20

申请号：US18595569

申请日：2024-03-05

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20240136247A1

公开(公告)日：2024-04-25

申请号：US18535726

申请日：2023-12-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Liangbiao CHEN ,  Yong LIU ,  Tzu-Hsuan CHENG ,  Stephen ST. GERMAIN ,  Roger ARBUTHNOT

IPC: H01L23/367 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H05K7/20

CPC classification number: H01L23/3675 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3735 ,  H01L24/32 ,  H05K7/2089 ,  H01L2224/32245 ,  H01L2224/84801 ,  H01L2924/13055

Abstract: In at least one aspect, a method can include shaping a block of flexible spacer material. The method can include shaping a portion of the block of flexible spacer material to receive a solid metal block. The method can include coupling the solid metal block to the portion of the block of flexible spacer material.

公开(公告)号：US20220415767A1

公开(公告)日：2022-12-29

申请号：US17929898

申请日：2022-09-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/40 ,  H01L23/00 ,  H01L25/065 ,  H01L23/367

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20200258739A1

公开(公告)日：2020-08-13

申请号：US16861615

申请日：2020-04-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Stephen ST. GERMAIN

IPC: H01L21/02 ,  H01L23/498 ,  H01L23/15 ,  H01L23/14 ,  H01L21/48 ,  H01L23/495 ,  H01L29/20 ,  H01L21/78

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

公开(公告)号：US20180254217A1

公开(公告)日：2018-09-06

申请号：US15446281

申请日：2017-03-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Gordon M. GRIVNA ,  Stephen ST. GERMAIN

IPC: H01L21/78 ,  H01L21/02 ,  H01L21/48 ,  H01L29/20 ,  H01L23/495

CPC classification number: H01L21/7806 ,  H01L21/02381 ,  H01L21/0254 ,  H01L21/4825 ,  H01L21/78 ,  H01L23/49562 ,  H01L29/2003

Abstract: A first semiconductor substrate contains a first semiconductor material, such as silicon. A second semiconductor substrate containing a second semiconductor material, such as gallium nitride or aluminum gallium nitride, is formed on the first semiconductor substrate. The first semiconductor substrate and second semiconductor substrate are singulated to provide a semiconductor die including a portion of the second semiconductor material supported by a portion of the first semiconductor material. The semiconductor die is disposed over a die attach area of an interconnect structure. The interconnect structure has a conductive layer and optional active region. An underfill material is deposited between the semiconductor die and die attach area of the interconnect structure. The first semiconductor material is removed from the semiconductor die and the interconnect structure is singulated to separate the semiconductor die. The first semiconductor material can be removed post interconnect structure singulation.

公开(公告)号：US20240203845A1

公开(公告)日：2024-06-20

申请号：US18592704

申请日：2024-03-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/367 ,  H01L23/40 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/49568 ,  H01L23/49582 ,  H01L24/80 ,  H01L25/0657

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

公开(公告)号：US20240128240A1

公开(公告)日：2024-04-18

申请号：US18398589

申请日：2023-12-28

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chee Hiong CHEW ,  Atapol PRAJUCKAMOL ,  Stephen ST. GERMAIN ,  Yusheng LIN

IPC: H01L25/07 ,  H01L23/00 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L25/071 ,  H01L23/367 ,  H01L24/32 ,  H01L25/50 ,  H01L2224/32245

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.