公开(公告)号：US09478677B2

公开(公告)日：2016-10-25

申请号：US14723993

申请日：2015-05-28

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Julien Pruvost ,  Romain Coffy

IPC: H01L31/0232 ,  H01L31/0203 ,  H01L31/18 ,  H01L31/02 ,  H01L27/146

CPC classification number: H01L31/0203 ,  H01L27/14618 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/1464 ,  H01L27/14683 ,  H01L31/02002 ,  H01L31/02327 ,  H01L31/18 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/15174 ,  H01L2924/16235

Abstract: An electronic device includes a substrate plate with a traversing passage. An electronic component, mounted to the substrate plate, includes an integrated circuit chip with an optical sensor and an opaque protective plate mounted above the sensor. The electronic component is mounted with the chip facing the substrate plate such that the protective plate is engaged with the traversing passage. Electrical connection elements extend between the chip and the substrate plate. An internal block of encapsulation material extends into the traversing passage of the substrate plate between the chip and the substrate plate so as to embed the electrical connection elements.

Abstract translation: 电子设备包括具有横向通道的基板。 安装到基板的电子部件包括具有安装在传感器上方的光学传感器和不透明保护板的集成电路芯片。 电子部件安装有芯片面向衬底板，使得保护板与横向通道接合。 电连接元件在芯片和基板之间延伸。 封装材料的内部块在芯片和衬底板之间延伸到衬底板的横向通道中，以嵌入电连接元件。

公开(公告)号：US20140206154A1

公开(公告)日：2014-07-24

申请号：US14221921

申请日：2014-03-21

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Romain Coffy ,  Yvon Imbs ,  Laurent Marechal

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/18 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/97 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/185 ,  H05K2201/10015 ,  H05K2201/10674 ,  H05K2203/1469 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor device includes a wafer having a frontside and a backside. The wafer is formed from at least one integrated circuit chip having an electrical connection frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. A passive component including at least one conductive plate and a dielectric plate is positioned adjacent the integrated circuit chip. An encapsulation block embeds the integrated circuit chip and the passive component, the block having a frontside co-planar with the wafer frontside and a backside co-planar with the wafer backside. An electrical connection is made between the electrical connection frontside and the passive component. That electrical connection includes connection lines placed on the wafer frontside and wafer backside. The electrical connection further includes at least one via passing through the encapsulation block.

Abstract translation: 半导体器件包括具有前侧和后侧的晶片。 晶片由至少一个集成电路芯片形成，该集成电路芯片具有与晶片前侧共面的电连接，以及与晶片背面共面的背面。 包括至少一个导电板和电介质板的无源部件位于集成电路芯片附近。 封装块嵌入集成电路芯片和无源部件，该块具有与晶片前侧共面的前侧和与晶片背面共面的背面。 在电连接前端和被动部件之间进行电连接。 该电连接包括放置在晶片正面和晶片背面上的连接线。 电连接还包括至少一个通过封装块的通孔。

公开(公告)号：US11641002B2

公开(公告)日：2023-05-02

申请号：US17199180

申请日：2021-03-11

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre Coullomb ,  Romain Coffy ,  Jean-Michel Riviere

IPC: G01S7/481 ,  H01L31/16

Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.

公开(公告)号：US11437306B2

公开(公告)日：2022-09-06

申请号：US17165295

申请日：2021-02-02

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Fabien Quercia

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01Q1/22

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

公开(公告)号：US11211772B2

公开(公告)日：2021-12-28

申请号：US16432576

申请日：2019-06-05

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Romain Coffy ,  Jean-Michel Riviere

IPC: H01S5/068 ,  H01S3/034 ,  H01S3/02 ,  H01S5/00 ,  H01S5/183

Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a barrel comprising a mounting for a diffuser; and a diffuser positioned in the mounting, wherein the barrel comprises first and second conducting columns and a fuse or conductive wire electrically coupling the first and second conducting columns. A portion of the fuse is mechanically fixed to the diffuser and/or the fuse being arranged to trap the diffuser in said mounting.

公开(公告)号：US10978607B2

公开(公告)日：2021-04-13

申请号：US16409714

申请日：2019-05-10

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Alexandre Coullomb ,  Romain Coffy ,  Jean-Michel Riviere

IPC: H01L31/16 ,  G01S7/481

Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.

公开(公告)号：US10965376B2

公开(公告)日：2021-03-30

申请号：US16218948

申请日：2018-12-13

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jean-Michel Riviere ,  Romain Coffy ,  Karine Saxod

IPC: H04B10/40 ,  H05K7/02 ,  H05K5/03 ,  H04B10/80 ,  H01L31/16 ,  H01L31/0203

Abstract: A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.

公开(公告)号：US09401349B2

公开(公告)日：2016-07-26

申请号：US14723893

申请日：2015-05-28

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Malta) Ltd ,  STMicroelectronics S.r.l.

Inventor： Angelo Crobu ,  Kenneth Fonk ,  Romain Coffy

IPC: G01P15/08 ,  H01L25/18 ,  G01L19/14 ,  H01L23/24 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  G01L19/0084 ,  G01L19/147 ,  G01L19/148 ,  H01L23/24 ,  H01L23/3157 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/1319 ,  H01L2224/16145 ,  H01L2224/26122 ,  H01L2224/26135 ,  H01L2224/29007 ,  H01L2224/29021 ,  H01L2224/29036 ,  H01L2224/32014 ,  H01L2224/32111 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48106 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/146 ,  H01L2924/16151 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A stack of chips is formed by a first integrated-circuit chip and a second integrated-circuit chip. The chips have opposing faces which are separated from each other by an interposed spacer. The spacer is fastened by adhesion to only one of the opposing faces. The opposing faces are fastened to each other by a local adhesive which is separate from spacer.

Abstract translation: 一堆芯片由第一集成电路芯片和第二集成电路芯片形成。 芯片具有通过插入的间隔件彼此分离的相对面。 间隔件通过粘合固定到只有一个相对的面。 相对的面通过与间隔物分离的局部粘合剂彼此紧固。

公开(公告)号：US20150102500A1

公开(公告)日：2015-04-16

申请号：US14512060

申请日：2014-10-10

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Romain Coffy ,  Rémi Brechignac

IPC: H01L23/00 ,  H01L23/522

CPC classification number: H01L24/33 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32146 ,  H01L2224/32225 ,  H01L2224/32235 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06575 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/144 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic system includes a first integrated-circuit chip and a second integrated-circuit chip. A first substrate wafer is positioned between the first and second integrated-circuit chips and configured with a first connection network to make electrical connection to the first integrated-circuit chip. A second substrate wafer, configured with a second connection network to make electrical connection to the second integrated-circuit chip, is positioned facing the first substrate wafer. The connection networks of the first and second substrate wafers are electrically connected through connection structures. A third substrate wafer, including a third connection network, is thermally in contact with the first integrated-circuit chip and electrically connected to the first connection network of the first substrate wafer through further connection structures. The further connection structure may be formed using another substrate wafer.

Abstract translation: 电子系统包括第一集成电路芯片和第二集成电路芯片。 第一衬底晶片位于第一和第二集成电路芯片之间并且配置有第一连接网络以与第一集成电路芯片进行电连接。 配置有与第二集成电路芯片进行电连接的第二连接网络的第二衬底晶片被定位成面向第一衬底晶片。 第一和第二衬底晶片的连接网络通过连接结构电连接。 包括第三连接网络的第三衬底晶片与第一集成电路芯片热接触，并通过另外的连接结构电连接到第一衬底晶片的第一连接网络。 另外的连接结构可以使用另一个衬底晶片形成。

公开(公告)号：US09006904B2

公开(公告)日：2015-04-14

申请号：US13654850

申请日：2012-10-18

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Dominique Marais ,  Jacques Chavade ,  Rémi Brechignac ,  Eric Saugier ,  Romain Coffy ,  Luc Petit

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/367 ,  H01L25/065 ,  H05K1/02 ,  H05K3/34

CPC classification number: H01L25/0652 ,  H01L23/3677 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0206 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053

Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.

Abstract translation: 电子封装包括具有互连网络的衬底晶片。 第一芯片固定到基板的前部，连接到互连网络并由主体封装。 第二芯片放置在基板晶片的背面，并通过设置在基板的背面和第二芯片的前侧之间的背面连接元件连接到互连网络。 前端连接元件放置在基板的正面并连接到互连网络。 连接元件延伸超出身体的正面。 封装可以安装在具有插入的导热材料的板上。