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公开(公告)号：US08929170B2
公开(公告)日：2015-01-06
申请号：US13773125
申请日：2013-02-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Soo Park , Bong-Soon Lim , Hyuk-Jun Yoo
Abstract: A power management method includes receiving a first command with first address indicating a first high power operation that is immediately executed in a first memory die, after receipt of the first command, receiving a second command with a second address indicating a second high power operation, such that an immediate execution of the second high power operation would overlap the first high power operation, and delaying execution of second high power operation through a first waiting period that ends upon completion of the first high power operation, while applying a reference voltage to a second word line of the second memory die indicated by the second address.
Abstract translation: 一种电源管理方法，包括：在接收到所述第一命令之后，接收到具有指示在第一存储器管芯中立即执行的第一高功率操作的第一地址的第一命令，接收到具有指示第二高功率操作的第二地址的第二命令， 使得第二高功率操作的立即执行将与第一高功率操作重叠，并且通过在第一高功率操作完成时结束的第一等待时段来延迟第二高功率操作的执行，同时将参考电压施加到 由第二地址指示的第二存储器管芯的第二字线。
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12.发明授权公开(公告)号：US10854250B2
公开(公告)日：2020-12-01
申请号：US15997964
申请日：2018-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jae-Yun Lee , Joon Soo Kwon , Byung Soo Kim , Su-Yong Kim , Sang-Soo Park , Il Han Park , Kang-Bin Lee , Jong-Hoon Lee , Na-Young Choi
IPC: G11C8/08 , G11C29/12 , G11C16/30 , G11C16/08 , G11C16/34 , G11C16/10 , G11C16/04 , G06F3/06 , G11C5/14 , G11C16/12 , G11C16/14 , G11C29/02
Abstract: A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.
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公开(公告)号：US10061538B2
公开(公告)日：2018-08-28
申请号：US15336014
申请日：2016-10-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Soo Park , Dong-Kyo Shim
CPC classification number: G06F3/0656 , G06F3/0604 , G06F3/0685 , G11C11/5628 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3459 , G11C2211/5642 , G11C2211/5643 , G11C2211/5644
Abstract: A memory device is provided as follows. A memory cell array includes a plurality of memory cells, and the plurality of memory cells are divided into a first memory group and a second memory group. A first page buffer group is coupled to the first memory group and includes a plurality of first page buffers. A second page buffer group is coupled to the second memory group and includes a plurality of second page buffers. The first page buffer group performs a first data processing operation on data stored in the first page buffer group and stores a result of the first data processing operation. The second page buffer group performs a second data processing operation on data stored in the second page buffer group and stores a result of the second data processing operation. The first and second data processing operations are performed at substantially the same.
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公开(公告)号：US09991007B2
公开(公告)日：2018-06-05
申请号：US15207774
申请日：2016-07-12
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Sang Lee , Sang-Soo Park , Dong-Kyo Shim
IPC: G11C29/12 , G11C7/10 , G11C7/12 , G11C7/14 , G11C7/22 , G11C8/10 , G11C29/56 , G11C11/56 , G11C29/42 , G11C29/52 , G11C16/04 , G11C16/26 , G11C29/50 , G11C29/04 , G11C27/02
CPC classification number: G11C29/1201 , G11C7/1006 , G11C7/1039 , G11C7/1057 , G11C7/106 , G11C7/12 , G11C7/14 , G11C7/222 , G11C8/10 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C27/02 , G11C29/42 , G11C29/50012 , G11C29/52 , G11C29/56008 , G11C2029/0411 , G11C2029/5004 , G11C2211/5642
Abstract: A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≤N, L>1, P≤M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.
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Patent Agency Ranking
公开(公告)号：US09852804B2
公开(公告)日：2017-12-26
申请号：US15281837
申请日：2016-09-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Chul Park , Hyun-Young Yoo , Sang-Soo Park
CPC classification number: G11C16/3431 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C29/021 , G11C29/028
Abstract: A method of operating a nonvolatile memory device that includes a three-dimensional (3D) memory cell array is provided as follows. A first read operation is performed on first memory cells connected to a first word line by using a first read voltage level. A read retry operation is, if the first read operation fails, performed on the first memory cells so that a read retry voltage level is set to a second read voltage level. A read offset table is determined based on a difference between the first read voltage level and the second read voltage level. The read offset table stores a plurality of read voltage offsets. A second read operation is performed on second memory cells connected to a second word line by using a third read voltage level determined using the read offset table.
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公开(公告)号：US09824765B2
公开(公告)日：2017-11-21
申请号：US15251090
申请日：2016-08-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sang-Soo Park , Yoon Kim , Won-Bo Shim
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/32 , G11C16/349
Abstract: A method of erasing a non-volatile memory device which includes a plurality of NAND strings is provided as follows. A first voltage is applied to each of word lines for a corresponding effective erasing execution time. An erase operation is performed on memory cells connected to each of the word lines for the corresponding effective erasing execution time. A second voltage is applied to each of at least some word lines among the word lines for a corresponding erasing-prohibited time after the corresponding effective erasing execution time elapses. A sum of the corresponding effective erasing execution time and the corresponding erasing-prohibited time for each of the at least some word lines is substantially equal to an erasure interval during which an erase operation is performed using the first voltage and the second voltage higher than the first voltage. The word lines are stacked on a substrate.
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公开(公告)号：US09812214B2
公开(公告)日：2017-11-07
申请号：US15340957
申请日：2016-11-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Dongkyo Shim , Sang-Soo Park
CPC classification number: G11C16/3445 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26
Abstract: A nonvolatile memory device may include a memory cell array, an address decoder circuit, a page buffer circuit, and a control logic circuit. An erase operation includes iteratively performing an erase loop which includes an erase section where an erase voltage is applied to the memory cells of the selected memory block and an erase verification section where the memory cells of the selected memory block are verified using an erase verification voltage. If the memory cells of the selected memory block are determined as an erase pass in the erase verification section, the control logic circuit monitors the memory cells of the selected memory block. If the monitored result indicates that the memory cells of the selected memory block are at an abnormal state, the control logic circuit applies an extra erase voltage to the memory cells of the selected memory block.
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公开(公告)号：US09812168B2
公开(公告)日：2017-11-07
申请号：US15044321
申请日：2016-02-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Doo-Hyun Kim , Jae-Hyun Kim , Byeong-Jun Kim , Sang-Soo Park , Jun-Soo Lee , Ho-Chul Hwang
IPC: H04N9/80 , H04N5/93 , G11B27/031
CPC classification number: G11B27/031
Abstract: The present disclosure provides an electronic device and method for playing image data. The method for playing back image data in an electronic device includes storing an audiovisual (A/V) data for a predetermined period of time in a memory of the electronic device. The electronic device plays back the A/V data, wherein upon playing back, by the electronic device, the A/V data comprises analyzing an audio signal of the A/V data dynamically to select one of a plurality of sound effects based on the analyzed audio signal. The A/V data is played back by applying the selected sound effect to at least a part of the A/V signal.
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公开(公告)号：US09384803B2
公开(公告)日：2016-07-05
申请号：US14468936
申请日：2014-08-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sang-Soo Park , Moosung Kim , Taekyun Kang
CPC classification number: G11C7/20 , G11C5/148 , G11C16/30 , G11C2207/2227
Abstract: A latch management method of a storage device includes permitting the storage device to enter a reduced power mode in which the storage device operates with a reduced power. The method includes reading initial latch data stored in the at least one nonvolatile memory device in response to the entering operation. The method includes setting latches associated with the at least one nonvolatile memory device based on the read initial latch data.
Abstract translation: 存储装置的锁存管理方法包括允许存储装置进入存储装置以降低的功率运行的降低功率模式。 该方法包括响应于输入操作读取存储在至少一个非易失性存储器件中的初始锁存数据。 该方法包括基于读取的初始锁存数据来设置与至少一个非易失性存储器件相关联的锁存器。
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