公开(公告)号：US10367096B2

公开(公告)日：2019-07-30

申请号：US15814925

申请日：2017-11-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Shinya Sasagawa ,  Satoru Okamoto ,  Motomu Kurata ,  Yuta Endo

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/66

Abstract: A semiconductor device which includes a transistor having a miniaturized structure is provided. A first insulator is provided over a stack in which a semiconductor, a first conductor, and a second conductor are stacked in this order. Over the first insulator, an etching mask is formed. Using the etching mask, the first insulator and the second conductor are etched until the first conductor is exposed. After etching the first conductor until the semiconductor is exposed so as to form a groove having a smaller width than the second conductor, a second insulator and a third conductor are formed sequentially.

公开(公告)号：US10164120B2

公开(公告)日：2018-12-25

申请号：US15576445

申请日：2016-05-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Motomu Kurata ,  Shinya Sasagawa ,  Katsuaki Tochibayashi ,  Satoru Okamoto ,  Akihisa Shimomura

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115 ,  H01L51/50 ,  H01L27/146 ,  H05B33/14 ,  G06F9/32 ,  G06K19/07 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L27/12 ,  G02F1/1368 ,  H01L27/32

Abstract: A transistor including a semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator is manufactured by forming a hard mask layer including a fourth conductor over the second insulator, a third insulator over the fourth conductor, forming an opening portion in the second insulator with the hard mask layer as the mask, eliminating the hard mask layer by forming the opening portion, and forming the first insulator and the first conductor in the opening portion.

公开(公告)号：US09978774B2

公开(公告)日：2018-05-22

申请号：US15420628

申请日：2017-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US09954113B2

公开(公告)日：2018-04-24

申请号：US15017831

申请日：2016-02-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Akihisa Shimomura ,  Satoru Okamoto ,  Yutaka Okazaki ,  Yoshinobu Asami ,  Hiroaki Honda ,  Takuya Tsurume

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/385 ,  H01L27/1225 ,  H01L29/0688 ,  H01L29/42384 ,  H01L29/78696

Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.

公开(公告)号：US09865712B2

公开(公告)日：2018-01-09

申请号：US15056356

申请日：2016-02-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/22 ,  H01L29/24 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/385 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/22 ,  H01L29/24 ,  H01L29/401 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/78 ,  H01L29/786 ,  H01L29/7869 ,  H01L29/78696

Abstract: A minute transistor is provided. A transistor with low parasitic capacitance is provided. A transistor having high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween. The second insulator has an opening and a side surface of the second insulator overlaps with a side surface of the first conductor in the opening with the first insulator positioned therebetween. Part of a surface of the second conductor and part of a surface of the third conductor are in contact with the first insulator in the opening. The oxide semiconductor overlaps with the second conductor and the third conductor.

公开(公告)号：US12156410B2

公开(公告)日：2024-11-26

申请号：US17629804

申请日：2020-07-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Tatsuya Onuki ,  Yuki Okamoto ,  Hideki Uochi ,  Satoru Okamoto ,  Hiromichi Godo ,  Kazuki Tsuda ,  Hitoshi Kunitake

IPC: H10B63/00 ,  H10B41/27 ,  H10B43/27

Abstract: A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

公开(公告)号：US12074224B2

公开(公告)日：2024-08-27

申请号：US17591690

申请日：2022-02-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/786 ,  C23C16/40 ,  C23C16/455 ,  H01L21/475 ,  H01L21/4757 ,  H01L21/67 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

公开(公告)号：US11943929B2

公开(公告)日：2024-03-26

申请号：US18129120

申请日：2023-03-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Hajime Kimura ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H10B43/27 ,  H01L29/24 ,  H01L29/51 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H10B43/27 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L29/24 ,  H01L29/513

Abstract: A semiconductor device with a large storage capacity per unit area is provided. The semiconductor device includes a first insulator including a first opening, a first conductor that is over the first insulator and includes a second opening, a second insulator that is over the first insulator and includes a third opening, and an oxide penetrating the first opening, the second opening, and the third opening. The oxide includes a first region at least in the first opening, a second region at least in the second opening, and a third region at least in the third opening. The resistances of the first region and the third region are lower than the resistance of the second region.

公开(公告)号：US10367005B2

公开(公告)日：2019-07-30

申请号：US15966231

申请日：2018-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Yuta Endo ,  Kiyoshi Kato ,  Satoru Okamoto

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8258 ,  H01L27/06 ,  H01L21/3105 ,  H01L21/3115 ,  H01L27/088 ,  H01L27/092

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US09954112B2

公开(公告)日：2018-04-24

申请号：US14995562

申请日：2016-01-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshinobu Asami ,  Yutaka Okazaki ,  Satoru Okamoto ,  Shinya Sasagawa

IPC: H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L21/475 ,  H01L29/66 ,  H01L21/4757 ,  H01L21/67 ,  C23C16/40 ,  C23C16/455 ,  H01L27/12 ,  H01L21/02

CPC classification number: H01L29/7869 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/0262 ,  H01L21/475 ,  H01L21/47573 ,  H01L21/67207 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/0649 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/78696

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.