公开(公告)号：US20090191684A1

公开(公告)日：2009-07-30

申请号：US12021062

申请日：2008-01-28

Applicant: Shau-Lin Shue ,  Ting-Chu Ko

Inventor： Shau-Lin Shue ,  Ting-Chu Ko

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for fabricating a semiconductor device is disclosed. First, a semiconductor substrate having a doped region(s) is provided. Thereafter, a pre-amorphous implantation process and neutral (or non-neutral) species implantation process is performed over the doped region(s) of the semiconductor substrate. Subsequently, a silicide is formed in the doped region(s). By conducting a pre-amorphous implantation combined with a neutral species implantation, the present invention reduces the contact resistance, such as at the contact area silicide and source/drain substrate interface.

Abstract translation: 公开了一种制造半导体器件的方法。 首先，提供具有掺杂区域的半导体衬底。 此后，在半导体衬底的掺杂区域上执行预非晶体注入工艺和中性（或非中性）物质注入工艺。 随后，在掺杂区域中形成硅化物。 通过进行与中性物质注入组合的预非晶注入，本发明降低了接触电阻，例如在接触面积硅化物和源极/漏极衬底界面处。

公开(公告)号：US20090091038A1

公开(公告)日：2009-04-09

申请号：US11867308

申请日：2007-10-04

Applicant: Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L23/52 ,  H01L21/4763

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.

Abstract translation: 本公开提供了一种用于制造集成电路的方法。 该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

公开(公告)号：US20080233839A1

公开(公告)日：2008-09-25

申请号：US11727119

申请日：2007-03-23

Applicant: Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

Inventor： Hsin-Hsien Lu ,  Liang-Guang Chen ,  Tien-I Bao ,  Shau-Lin Shue

IPC: C25F3/30

CPC classification number: B24B37/22 ,  B24B37/042 ,  B24B37/24

Abstract: Embodiments of a polisher for chemical mechanical planarization. The polisher includes a polishing pad structure containing a first reactant therein, and a second reactant in a polishing environment over the polishing pad structure. The first reactant and the second reactant react endothermically upon contact when polishing a wafer surface between the polishing pad structure and the polishing environment.

Abstract translation: 用于化学机械平面化的抛光机的实施例。 抛光机包括在其中包含第一反应物的抛光垫结构和在抛光环境中的抛光垫结构上的第二反应物。 当抛光抛光垫结构和抛光环境之间的晶片表面时，第一反应物和第二反应物在接触时发生吸热反应。

公开(公告)号：US07405151B2

公开(公告)日：2008-07-29

申请号：US11420900

申请日：2006-05-30

Applicant: Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Gin Jei Wang ,  Chao-Hsien Peng ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28562 ,  H01L21/31625 ,  H01L23/482 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor device is described. An opening is formed in a first dielectric layer, exposing an active region of the transistor, and an atomic layer deposited (ALD) TaN barrier is conformably formed in the opening, at a thickness less than 20 Å. A copper layer is formed over the atomic layer deposited (ALD) TaN barrier to fill the opening.

Abstract translation: 对半导体装置的形成方法进行说明。 在第一电介质层中形成开口，暴露晶体管的有源区，并且在开口中以厚度小于等于一致地形成原子层沉积（ALD）TaN势垒。 在原子层沉积（ALD）TaN势垒上形成铜层以填充开口。

公开(公告)号：US20080121929A1

公开(公告)日：2008-05-29

申请号：US11523683

申请日：2006-09-19

Applicant: Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

Inventor： Jerry Lai ,  Chii-Ming Wu ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC: H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/26506 ,  H01L21/2652 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66621 ,  H01L29/7848 ,  Y10S438/933

Abstract: A semiconductor structure includes a first silicon-containing layer comprising an element selected from the group consisting essentially of carbon and germanium wherein the silicon-containing layer has a first atomic percentage of the element to the element and silicon, a second silicon-containing layer comprising the element over the first silicon-containing layer, and a silicide layer on the second silicon-containing layer. The element in the second silicon-containing layer has a second atomic percentage of the element to the element and silicon, wherein the second atomic percentage is substantially lower than the first atomic percentage.

公开(公告)号：US20080057211A1

公开(公告)日：2008-03-06

申请号：US11468142

申请日：2006-08-29

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Hung-Wen Su ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: B05C3/00 ,  B05D1/18 ,  C25D5/00

CPC classification number: C25D5/00 ,  C25D5/04 ,  C25D17/001 ,  C25D21/12

Abstract: A method for plating includes positioning a substrate facing a plating solution. The method also includes immersing the substrate into the plating solution while plating a layer of material over a surface of the substrate, wherein an immersion speed of the substrate is about 100 millimeters per second (mm/s) or more while at least one portion of the substrate contacts the plating solution.

Abstract translation: 电镀方法包括定位面向电镀液的基板。 该方法还包括将衬底浸入电镀溶液中，同时在衬底的表面上镀覆一层材料，其中衬底的浸入速度为约100毫米/秒（mm / s）或更多，而至少一部分 基板接触电镀液。

公开(公告)号：US07312531B2

公开(公告)日：2007-12-25

申请号：US11261200

申请日：2005-10-28

Applicant: Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

Inventor： Hui-Lin Chang ,  Yung-Cheng Lu ,  Chung-Chi Ko ,  Pi-Tsung Chen ,  Shau-Lin Shue ,  Chien-Hsueh Shih ,  Hung-Wen Su ,  Ming-Hsing Tsai

IPC: H01L29/40 ,  H01L21/44

CPC classification number: H01L23/53276 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.

公开(公告)号：US20070284678A1

公开(公告)日：2007-12-13

申请号：US11838376

申请日：2007-08-14

Applicant: Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

Inventor： Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

IPC: H01L21/3205 ,  H01L29/45

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L21/28097 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

Abstract translation: 一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层 使用包括金属和硅的靶。 然后可以将金属硅化物层退火。

公开(公告)号：US07282450B2

公开(公告)日：2007-10-16

申请号：US10733722

申请日：2003-12-11

Applicant: Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

Inventor： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

Abstract: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

Abstract translation: 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

公开(公告)号：US20070221993A1

公开(公告)日：2007-09-27

申请号：US11389309

申请日：2006-03-27

Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

Abstract: A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.

Abstract translation: 提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层 在栅极区域和半导体器件的有源区中。