公开(公告)号：US20220278013A1

公开(公告)日：2022-09-01

申请号：US17747900

申请日：2022-05-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Chun-Chang Ting ,  Chi-Jen Chen

IPC: H01L23/31 ,  H01L21/56

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

公开(公告)号：US20210074603A1

公开(公告)日：2021-03-11

申请号：US16734612

申请日：2020-01-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Chun-Chang Ting ,  Chi-Jen Chen

IPC: H01L23/31 ,  H01L21/56

Abstract: A method for fabricating an electronic package is provided. A filling material is formed in an interval S, at which a plurality of electronic components disposed on a carrying structure are spaced apart from one another. The filling material acts as a spacer having a groove, and the groove acts as a stress buffering region. Therefore, the electronic components can be prevented from being broken due to stress concentration.

公开(公告)号：US09659806B2

公开(公告)日：2017-05-23

申请号：US14810523

申请日：2015-07-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227

Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.

公开(公告)号：US09502335B2

公开(公告)日：2016-11-22

申请号：US14487548

申请日：2014-09-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chieh-Lung Lai ,  Hsien-Wen Chen ,  Hong-Da Chang ,  Mao-Hua Yeh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/49 ,  H01L25/10 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/85005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15323 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00

Abstract: A package structure is provided, which includes: a chip carrier having a plurality of conductive connection portions; at least an electronic element disposed on the chip carrier; a plurality of conductive wires erectly positioned on the conductive connection portions, respectively; an encapsulant formed on the chip carrier for encapsulating the conductive wires and the electronic element, wherein one ends of the conductive wires are exposed from the encapsulant; and a circuit layer formed on the encapsulant and electrically connected to exposed ends of the conductive wires. According to the present invention, the conductive wires serve as an interconnection structure. Since the wire diameter of the conductive wires is small and the pitch between the conductive wires can be minimized, the present invention reduces the size of the chip carrier and meets the miniaturization requirement.

Abstract translation: 提供一种封装结构，其包括：具有多个导电连接部分的芯片载体; 至少设置在所述芯片载体上的电子元件; 多个导线分别竖立设置在导电连接部分上; 形成在所述芯片载体上用于封装所述导线和所述电子元件的密封剂，其中所述导线的一端从所述密封剂露出; 以及形成在密封剂上并电连接到导线的露出端的电路层。 根据本发明，导线用作互连结构。 由于导线的线径小，导线之间的间距可以最小化，因此本发明可以减小芯片载体的尺寸并满足小型化要求。

公开(公告)号：US20160141227A1

公开(公告)日：2016-05-19

申请号：US14940554

申请日：2015-11-13

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chun-Tang Lin ,  Shih-Ching Chen ,  Yi-Che Lai ,  Hong-Da Chang ,  Hung-Wen Liu ,  Yi-Wei Liu ,  Hsi-Chang Hsu

IPC: H01L23/48 ,  H01L23/528 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.

Abstract translation: 提供一种制造封装结构的方法，其包括：提供其上具有电路层的第一载体; 在所述电路层上形成多个导电柱，并且至少在所述第一载体上布置电子元件; 在所述第一载体上形成密封剂以封装所述导电柱，所述电路层和所述电子元件; 并且移除第一载体，从而分配用于形成导电柱的传统开孔工艺，从而降低制造成本。

公开(公告)号：US20160071784A1

公开(公告)日：2016-03-10

申请号：US14810523

申请日：2015-07-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Shih-Kuang Chiu

IPC: H01L23/48 ,  H01L23/528 ,  H01L21/683 ,  H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68368 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227

Abstract: A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches.

Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装包括基极层，多个导电柱，半导体元件和封装。 基层具有相对的第一和第二表面和接收部分。 导电柱形成在第二表面上。 每个导电柱具有第一和第二端子，并且第二端子远离基底层的第二表面。 半导体元件被容纳在接收部分中，并且具有相对的有源和无源表面，并且有源表面从第一表面露出。 封装形成在第二表面上，封装导电柱和半导体元件，并且具有相对的第三和第四表面，并且导电柱的第二端子从第四表面露出。 半导体封装设置有具有细间距的导电柱。

公开(公告)号：US08878356B2

公开(公告)日：2014-11-04

申请号：US13660200

申请日：2012-10-25

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Hong-Da Chang ,  Cheng-Hsiang Liu ,  Kuang-Wei Huang ,  Chun-Hung Lin ,  Hsin-Yi Liao

IPC: H01L23/48 ,  H01L23/22 ,  H01L23/24 ,  H01L23/051 ,  H01L23/053 ,  H01L23/043

CPC classification number: H01L23/051 ,  B81B7/0064 ,  B81B2207/092 ,  B81C2203/0154 ,  H01L23/043 ,  H01L23/053 ,  H01L24/48 ,  H01L2224/48 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A package structure is provided, including: a substrate having a ground pad and an MEMS element; a lid disposed on the substrate for covering the MEMS element; a wire segment electrically connected to the ground pad; an encapsulant encapsulating the lid and the wire segment; and a circuit layer formed on the encapsulant and electrically connected to the wire segment and the lid so as to commonly ground the substrate and the lid, thereby releasing accumulated electric charges on the lid so as to improve the reliability of the MEMS system and reduce the number of I/O connections.

Abstract translation: 提供一种封装结构，包括：具有接地焊盘和MEMS元件的衬底; 设置在所述基板上用于覆盖所述MEMS元件的盖; 电连接到接地垫的线段; 封装盖和线段的密封剂; 以及形成在密封剂上并电连接到线段和盖子上的电路层，以便共同接地衬底和盖子，从而释放盖上的积累的电荷，从而提高MEMS系统的可靠性并减少 I / O连接数。

公开(公告)号：US12125828B2

公开(公告)日：2024-10-22

申请号：US18464855

申请日：2023-09-11

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chi-Ching Ho ,  Bo-Hao Ma ,  Yu-Ting Xue ,  Ching-Hung Tseng ,  Guan-Hua Lu ,  Hong-Da Chang

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/13 ,  H01L2225/06541

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

公开(公告)号：US11923337B2

公开(公告)日：2024-03-05

申请号：US16554779

申请日：2019-08-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chi-Ching Ho ,  Bo-Hao Ma ,  Yu-Ting Xue ,  Ching-Hung Tseng ,  Guan-Hua Lu ,  Hong-Da Chang

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/5226 ,  H01L24/13 ,  H01L2225/06541

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

公开(公告)号：US11600571B2

公开(公告)日：2023-03-07

申请号：US17125195

申请日：2020-12-17

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Jun-Chang Ding ,  Hong-Da Chang ,  Hsi-Chang Hsu

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/532 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: An electronic package, a packaging substrate, and methods for fabricating the same are disposed. The electronic package includes a circuit structure having a first side and a second side opposing the first side, an electronic component disposed on the first side of the circuit structure, an encapsulation layer formed on the first side of the circuit structure and encapsulating the electronic component, a metal structure disposed on the second side of the circuit structure, and a plurality of conductive elements disposed on the metal structure. The plurality of conductive elements are disposed on the metal structure, rather than disposed on the circuit structure directly. Therefore, the bonding between the conductive elements and the circuit structure is improved, to avoid the plurality of conductive elements from being peeled.