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    CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF
    13.
    发明申请
    CHIP-LEVEL UNDERFILL PROCESS AND STRUCTURES THEREOF 失效
    芯片级底层工艺及其结构

    公开(公告)号：US20100003786A1

    公开(公告)日：2010-01-07

    申请号：US12166286

    申请日：2008-07-01

    申请人： Claudius Feger ,  Nancy C. LaBianca

    发明人： Claudius Feger ,  Nancy C. LaBianca

    IPC分类号： H01L21/00

    CPC分类号： H01L21/563 ,  H01L23/544 ,  H01L24/29 ,  H01L24/75 ,  H01L24/81 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81121 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

    摘要： A process comprises forming a first electrical interconnect structure on a surface of a singulated semiconductor chip having an alignment pattern. The alignment pattern is scanned and stored in a scanning device prior to application of a curable underfill coating to the surface of the singulated semiconductor chip. This is followed by applying a curable underfill coating to the surface of the singulated semiconductor chip to produce a coated semiconductor chip. The process also includes a step of delivering the scanned and stored alignment pattern to an alignment and joining device positioned adjacent to and operatively associated with a substrate having a second electrical interconnect structure alignable to make electrical contact with the first electrical interconnect structure. The coated semiconductor chip is placed in the alignment and joining device so that when the scanned and stored alignment pattern is activated the alignment and joining device positions the coated semiconductor chip so that the first electrical interconnect structure is aligned to make electrical contact with the second electrical interconnect structure. This is followed by activating the alignment and joining device to join the coated semiconductor chip to the substrate so that the first electrical interconnect structure is in electrical contact with the second electrical interconnect structure. In one embodiment, the first electrical interconnect structure is placed on a surface of a semiconductor chip array in a wafer to produce the electrically connectable semiconductor structure which is followed by dicing to produce at least one of the singulated semiconductor chips. Another embodiment comprises aligning the fist and second electrical interconnect structures prior to applying the curable underfill coating.

    摘要翻译： 一种方法包括在具有对准图案的单片半导体芯片的表面上形成第一电互连结构。 在将可固化的底部填充涂层施加到单片半导体芯片的表面之前，对准图案被扫描并存储在扫描装置中。 然后将可固化的底部填充涂层施加到单片化半导体芯片的表面以制造涂覆的半导体芯片。 该过程还包括将扫描和存储的对准图案递送到与具有可与第一电互连结构电接触的第二电互连结构的基板相邻并且可操作地相关联的对准和接合装置的步骤。 涂覆的半导体芯片被放置在对准和接合装置中，使得当扫描和存储的对准图案被激活时，对准和接合装置将涂覆的半导体芯片定位，使得第一电互连结构对准以与第二电气 互连结构。 然后激活对准和接合装置以将涂覆的半导体芯片连接到基板，使得第一电互连结构与第二电互连结构电接触。 在一个实施例中，将第一电互连结构放置在晶片中的半导体芯片阵列的表面上，以产生可电连接的半导体结构，随后进行切割以产生至少一个单片半导体芯片。 另一个实施例包括在施加可固化底部填充涂层之前对齐第一和第二电互连结构。

    Heat transfer control structures using thermal phonon spectral overlap
    15.
    发明申请
    Heat transfer control structures using thermal phonon spectral overlap 有权
    热传导控制结构使用热声子光谱重叠

    公开(公告)号：US20070230135A1

    公开(公告)日：2007-10-04

    申请号：US11395857

    申请日：2006-03-31

    申请人： Claudius Feger ,  Maurice McGlashan-Powell ,  Ijeoma Nnebe

    发明人： Claudius Feger ,  Maurice McGlashan-Powell ,  Ijeoma Nnebe

    IPC分类号： H05K7/20

    CPC分类号： H01L23/3735 ,  H01L23/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A heat transfer control structure and a method for fabrication thereof includes at least one heat transfer control layer interposed between and contacting a heat source material and a heat sink material. The at least one heat transfer control layer is selected predicated upon thermal phonon spectra overlap between the heat source material, the at least one heat transfer control layer and the heat sink material. The at least one heat transfer control layer may enhance or retard heat transfer between the heat source material and the heat sink material. The at least one heat transfer control layer may be selected based upon a value of a thermal phonon correlating parameter such as a Debye temperature, a density or a lattice constant.

    摘要翻译： 传热控制结构及其制造方法包括插入在热源材料和散热材料之间并与之接触的至少一个传热控制层。 根据热源材料，至少一个传热控制层和散热材料之间的热声子光谱重叠来选择至少一个传热控制层。 至少一个传热控制层可以增强或延缓热源材料和散热材料之间的热传递。 可以基于诸如德拜温度，密度或晶格常数的热声子相关参数的值来选择至少一个传热控制层。

    Flat panel display containing black matrix polymer
    19.
    发明授权
    Flat panel display containing black matrix polymer 失效
    含黑色矩阵聚合物的平板显示器

    公开(公告)号：US5619357A

    公开(公告)日：1997-04-08

    申请号：US466317

    申请日：1995-06-06

    申请人： Marie Angelopoulos ,  Ali Afzali-Ardakani ,  Claudius Feger ,  Chandrasekhar Narayan

    发明人： Marie Angelopoulos ,  Ali Afzali-Ardakani ,  Claudius Feger ,  Chandrasekhar Narayan

    IPC分类号： G02F1/1335

    CPC分类号： G02F1/133512

    摘要： A thin film transistor display that comprises a black matrix polymer layer, comprising a polymer having an optical density of at least about 0.8 per .mu.m and being self-absorbent of visible light and being selected from the group consisting of substituted and unsubstituted polyanilines, substituted and unsubstituted polyparaphenylenevinylenes, substituted and unsubstituted polythiophenes, substituted and unsubstituted polyazines, substituted and unsubstituted polyparaphenylenes, substituted and unsubstituted polyfuranes, substituted and unsubstituted polypyrroles, substituted and unsubstituted polyselenophene, substituted and unsubstituted poly-p-phenylene sulfides and substituted and unsubstituted polyacetylenes, and mixtures thereof, and copolymers thereof. The layer also comprises one or more pigments. The resistivity of the black matrix composite is 10E12 to 10E14 ohm cm.

    摘要翻译： 一种薄膜晶体管显示器，其包括黑矩阵聚合物层，其包含光密度为至少约0.8每μm的聚合物，并且是可吸收的可见光，并且选自取代和未取代的聚苯胺，取代的 取代和未取代的聚噻吩，取代和未取代的聚噻吩，取代和未取代的聚嗪，取代和未取代的聚对苯二烯，取代和未取代的聚呋喃，取代和未取代的聚吡咯，取代和未取代的聚硒吩，取代和未取代的聚对苯硫醚和取代和未取代的聚乙炔， 其混合物，及其共聚物。 该层还包含一种或多种颜料。 黑色矩阵复合材料的电阻率为10E12至10E14欧姆厘米。