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    IMPLIED FENCE ON STREAM OPEN
    11.
    发明申请
    IMPLIED FENCE ON STREAM OPEN 有权

    公开(公告)号：US20210216316A1

    公开(公告)日：2021-07-15

    申请号：US17216821

    申请日：2021-03-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Naveen BHORIA ,  Kai CHIRCA ,  Timothy D. ANDERSON ,  Duc BUI ,  Abhijeet A. CHACHAD ,  Son Hung TRAN

    IPC: G06F9/30 ,  G06F9/38 ,  G06F11/00 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/32 ,  G06F11/10 ,  G06F9/345

    Abstract: Techniques related to executing a plurality of instructions by a processor comprising receiving a first instruction configured to cause the processor to output a first data value to a first address in a first data cache, outputting, by the processor, the first data value to a second address in a second data cache, receiving a second instruction configured to cause a streaming engine associated with the processor to prefetch data from the first data cache, determining that the first data value has not been outputted from the second data cache to the first data cache, stalling execution of the second instruction, receiving an indication, from the second data cache, that the first data value has been output from the second data cache to the first data cache, and resuming execution of the second instruction based on the received indication.

    VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED PERFORMANCE
    12.
    发明申请
    VIRTUAL NETWORK PRE-ARBITRATION FOR DEADLOCK AVOIDANCE AND ENHANCED PERFORMANCE 审中-公开

    公开(公告)号：US20200117618A1

    公开(公告)日：2020-04-16

    申请号：US16653378

    申请日：2019-10-15

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Matthew David PIERSON ,  Daniel WU ,  Kai CHIRCA

    IPC: G06F13/16

    Abstract: A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

    EVENT HANDLING IN PIPELINE EXECUTE STAGES
    15.
    发明申请
    EVENT HANDLING IN PIPELINE EXECUTE STAGES 有权

    公开(公告)号：US20210124589A1

    公开(公告)日：2021-04-29

    申请号：US17079105

    申请日：2020-10-23

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai CHIRCA ,  Timothy D. ANDERSON ,  Paul Daniel GAUVREAU

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/54

    Abstract: A method includes receiving an execute packet that includes a first instruction and a second instruction and executing the first instruction and the second instruction using a pipeline. Executing the first and second instructions includes storing a result of the first instruction in a holding register; determining whether an event that interrupts execution of the execute packet occurs prior to completion of the executing of the second instruction; and based on the event not occurring, committing the result of the first instruction after completion of the executing of the second instruction.

    NESTED LOOP CONTROL
    17.
    发明申请
    NESTED LOOP CONTROL 审中-公开

    公开(公告)号：US20200371762A1

    公开(公告)日：2020-11-26

    申请号：US16983429

    申请日：2020-08-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai CHIRCA ,  Timothy D. ANDERSON ,  Todd T. HAHN ,  Alan L. DAVIS

    IPC: G06F8/41 ,  G06F5/06 ,  G06F9/30

    Abstract: A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

    SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS
    18.
    发明申请
    SLOT/SUB-SLOT PREFETCH ARCHITECTURE FOR MULTIPLE MEMORY REQUESTORS 审中-公开

    公开(公告)号：US20200057723A1

    公开(公告)日：2020-02-20

    申请号：US16552418

    申请日：2019-08-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kai CHIRCA ,  Joseph R. M. ZBICIAK ,  Matthew D. PIERSON

    IPC: G06F12/0897 ,  G06F12/0862 ,  G06F12/0811

    Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

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