公开(公告)号：US10553717B2

公开(公告)日：2020-02-04

申请号：US15138955

申请日：2016-04-26

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Hideaki Kawahara ,  Simon John Molloy ,  Satoshi Suzuki ,  John Manning Savidge Neilson

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L21/311 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/786

Abstract: A semiconductor device includes a medium voltage MOSFET having a vertical drain drift region between RESURF trenches containing field plates which are electrically coupled to a source electrode of the MOSFET. A split gate with a central opening is disposed above the drain drift region between the RESURF trenches. A two-level LDD region is disposed below the central opening in the split gate. A contact metal stack makes contact with a source region at lateral sides of the triple contact structure, and with a body contact region and the field plates in the RESURF trenches at a bottom surface of the triple contact structure. A perimeter RESURF trench surrounds the MOSFET. A field plate in the perimeter RESURF trench is electrically coupled to the source electrode of the MOSFET. An integrated snubber may be formed in trenches formed concurrently with the RESURF trenches.

公开(公告)号：US20170301596A1

公开(公告)日：2017-10-19

申请号：US15634472

申请日：2017-06-27

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Jonathan Almeria Noquil ,  Tom Grebs ,  Simon John Molloy

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/13 ,  H01L23/373 ,  H01L23/00

CPC classification number: H01L23/147 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/13 ,  H01L23/3738 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/06181 ,  H01L2224/32225 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/15153 ,  H01L2924/157

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

公开(公告)号：US20170179278A1

公开(公告)日：2017-06-22

申请号：US15248521

申请日：2016-08-26

Applicant: Texas Instruments Incorporated

Inventor： David J Baldwin ,  Gary Eugene Daum ,  Simon John Molloy ,  Abidur Rahman

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L21/225

CPC classification number: H01L29/7815 ,  H01L21/2253 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/0266 ,  H01L27/027 ,  H01L29/0634 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66719 ,  H01L29/7811

Abstract: A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches.

公开(公告)号：US20170062573A1

公开(公告)日：2017-03-02

申请号：US15347325

申请日：2016-11-09

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。

公开(公告)号：US20160163804A1

公开(公告)日：2016-06-09

申请号：US14563706

申请日：2014-12-08

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/40 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/404 ,  H01L21/763 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7802 ,  H01L29/7803 ,  H01L29/7811 ,  H01L29/7827 ,  H01L29/783 ,  H01L29/7832

Abstract: A vertical, high-voltage MOS transistor, which has a source region, a body contact region, and a number of trenches structures with field plates, and a method of forming the MOS transistor increase the on-state resistance of the MOS transistor by reducing the trench pitch. Trench pitch can be reduced with metal contacts that simultaneously touch the source regions, the body contact regions, and the field plates. Trench pitch can also be reduced with a gate that increases the size of the LDD region.

Abstract translation: 具有源区域，体接触区域和多个具有场板的沟槽结构的垂直高压MOS晶体管，以及形成MOS晶体管的方法通过减少MOS晶体管的导通电阻来降低 沟渠。 可以通过同时接触源区域，身体接触区域和场板的金属触点来减少沟槽间距。 也可以通过增加LDD区域的尺寸的栅极来减小沟槽间距。

公开(公告)号：US20160133616A1

公开(公告)日：2016-05-12

申请号：US14737072

申请日：2015-06-11

Applicant: Texas Instruments Incorporated

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/042 ,  H01L31/0216 ,  H01L25/00 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L31/028 ,  H01L27/082

CPC classification number: H01L25/167 ,  H01L21/50 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49844 ,  H01L24/83 ,  H01L25/18 ,  H01L25/50 ,  H01L27/082 ,  H01L27/088 ,  H01L29/0657 ,  H01L31/02008 ,  H01L31/02168 ,  H01L31/028 ,  H01L31/042 ,  H01L31/1804 ,  H01L31/1868 ,  H01L2224/83851 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/04642 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/10155 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1425 ,  H01L2924/1427 ,  H01L2924/15

Abstract: A self-powered electronic system comprises a first chip (401) of single-crystalline semiconductor embedded in a second chip (302) of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container (330) bordered by ridges (331). The flat side (335) of the slab includes a heavily n-doped region (314) forming a pn-junction (315) with the p-type bulk. A metal-filled deep silicon via (350) through the p-type ridge (331) connects the n-region with the terminal (322) on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

Abstract translation: 一种自供电的电子系统包括：嵌入第二芯片（302）中的单晶半导体的第一芯片（401），该第二芯片形成为与脊状接合的容器。 组装的芯片被嵌套，并形成电子器件，该电子器件依次组装在由p型掺杂的低级硅片形成的平板中，该片状物作为与脊（331）相邻的容器（330）。 板坯的平坦侧面（335）包括形成具有p型体积的pn结（315）的大量n掺杂区域（314）。 通过p型脊（331）的金属填充的深硅通孔（350）将p区域作为阳极将n区与作为阳极的阳极的脊表面上的端子（322）连接。 pn结上的电压用作器件的电源。

公开(公告)号：US20150357459A1

公开(公告)日：2015-12-10

申请号：US14299040

申请日：2014-06-09

Applicant: Texas Instruments Incorporated

Inventor： Christopher Boguslaw Kocon ,  Simon John Molloy ,  John Manning Savidge Neilson ,  Hideaki Kawahara

IPC: H01L29/78 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7804 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66727 ,  H01L29/7811

Abstract: A semiconductor device includes a vertical drift region over a drain contact region, abutted on opposite sides by RESURF trenches. A split gate is disposed over the vertical drift region. A first portion of the split gate is a gate of an MOS transistor and is located over a body of the MOS transistor over a first side of the vertical drift region. A second portion of the split gate is a gate of a channel diode and is located over a body of the channel diode over a second, opposite, side of the vertical drift region. A source electrode is electrically coupled to a source region of the channel diode and a source region of the MOS transistor.

Abstract translation: 半导体器件包括在漏极接触区域上方的垂直漂移区域，通过RESURF沟槽抵靠在相对侧上。 分离栅极设置在垂直漂移区域上。 分离栅极的第一部分是MOS晶体管的栅极，并且位于垂直漂移区域的第一侧上的MOS晶体管的主体上方。 分离栅极的第二部分是沟道二极管的栅极，并且位于垂直漂移区域的第二相对侧上的沟道二极管的主体上方。 源电极电耦合到沟道二极管的源极区域和MOS晶体管的源极区域。

公开(公告)号：US11177246B2

公开(公告)日：2021-11-16

申请号：US16546475

申请日：2019-08-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Osvaldo Jorge Lopez ,  Walter Hans Paul Schroen ,  Jonathan Almeria Noquil ,  Thomas Eugene Grebs ,  Simon John Molloy

IPC: H01L25/16 ,  H01L31/028 ,  H01L31/042 ,  H01L31/0216 ,  H01L27/082 ,  H01L27/088 ,  H01L31/18 ,  H01L31/02 ,  H01L25/00 ,  H01L29/06 ,  H01L23/053 ,  H01L23/06 ,  H01L23/13 ,  H01L23/14 ,  H01L21/50 ,  H01L23/00 ,  H01L25/18 ,  H01L25/04 ,  H01L23/498

Abstract: A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

公开(公告)号：US20180226502A1

公开(公告)日：2018-08-09

申请号：US15427489

申请日：2017-02-08

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Christopher Boguslaw Kocon ,  Seetharaman Sridhar ,  Simon John Molloy ,  Satoshi Suzuki

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7802 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7811

Abstract: A device includes a transistor formed on a substrate. The transistor includes an n-type drain contact layer, an n-type drain layer, an oxide layer, a p-type body region, a p-type terminal region, body trenches, and terminal trenches. The n-type drain contact layer is near a bottom surface of the substrate. The n-type drain layer is positioned on the n-type drain contact layer. The oxide layer circumscribes a transistor region. The p-type body region is positioned within the transistor region. The p-type terminal region extends from under the oxide layer to an edge of the transistor region, thereby forming a contiguous junction with the p-type body region. The body trenches is within the transistor region and interleaves with the p-type body region, whereas the terminal trenches is outside the transistor region and interleaves with the p-type terminal region.

公开(公告)号：US09905638B1

公开(公告)日：2018-02-27

申请号：US15281865

申请日：2016-09-30

Applicant: Texas Instruments Incorporated

Inventor： Tatsuya Tominari ,  Satoshi Suzuki ,  Seetharaman Sridhar ,  Christopher Boguslaw Kocon ,  Simon John Molloy ,  Hideaki Kawahara

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/167

CPC classification number: H01L29/0634 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/167

Abstract: A method of forming a semiconductor device includes etching a high aspect ratio, substantially perpendicular trench in a semiconductor region doped with a first dopant having first conductivity type and performing a first cycle for depositing silicon doped with a second dopant on an inner surface of the high aspect ratio, substantially perpendicular trench, the first cycle comprising alternately depositing silicon at a first constant pressure and etching the deposited silicon at an etching pressure that ramps up from a first value to a second value, the second dopant having a second conductivity type that is opposite from the first conductivity type.