公开(公告)号：US20180096872A1

公开(公告)日：2018-04-05

申请号：US15831806

申请日：2017-12-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nai-Han Cheng ,  Chi-Ming Yang

IPC: H01L21/67 ,  G01B11/16 ,  G01B11/24 ,  H01L21/66 ,  G01B11/14 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L21/67288 ,  G01B11/14 ,  G01B11/161 ,  G01B11/2441 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L23/562 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.

公开(公告)号：US20170306485A1

公开(公告)日：2017-10-26

申请号：US15138473

申请日：2016-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Chieh Lee ,  Chi-Ming Yang ,  Lin-Jung Wu

IPC: C23C16/448 ,  C23C16/44 ,  C23C16/40

CPC classification number: C23C16/4482 ,  C23C16/405 ,  C23C16/4402

Abstract: A method of solid precursor delivery for a vapor deposition process is provided. In some embodiments, a precursor ampoule is provided including a solid precursor arranged in the precursor ampoule. A solvent is added to the precursor ampoule including one or more ionic liquids to dissolve chemical species of the solid precursor and to form a liquid precursor. A carrier gas is applied into the liquid precursor through an inlet of the precursor ampoule. A gas precursor is generated at an upper region of the precursor ampoule by vaporization of the liquid precursor. The chemical species of the solid precursor are delivered into a vapor deposition chamber by the carrier gas. The chemical species of the solid precursor is deposited onto a substrate within the vapor deposition chamber.

公开(公告)号：US09579697B2

公开(公告)日：2017-02-28

申请号：US13706403

申请日：2012-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jyh-Shiou Hsu ,  Chi-Ming Yang ,  Kuo-Sheng Chuang

IPC: B08B9/46 ,  B08B9/08 ,  H01L21/67 ,  H01L21/673

CPC classification number: B08B9/46 ,  B08B9/0861 ,  H01L21/67051 ,  H01L21/67207 ,  H01L21/67253 ,  H01L21/67393

Abstract: A system for cleaning a container such as semiconductor wafer carrier includes a housing, a cleaning unit in the housing, an analyzing unit within the housing, and a vacuum unit within the housing. The cleaning unit comprises a cleaning chamber, and is configured to spray a cleaning medium into the container in the cleaning chamber and dry the container. The analyzing unit is configured to analyze air inside the container coming out of the cleaning chamber, and provide a testing result for each ingredient of possible airborne molecular contamination (AMC) and humidity. The vacuum unit comprises a vacuum chamber configured to apply vacuum onto a container when the testing result for an ingredient is higher than a respective threshold.

Abstract translation: 用于清洁诸如半导体晶片载体的容器的系统包括壳体，壳体中的清洁单元，壳体内的分析单元以及壳体内的真空单元。 清洁单元包括清洁室，并且构造成将清洁介质喷射到清洁室中的容器中并干燥容器。 分析单元被配置为分析来自清洁室的容器内的空气，并且为每种可能的空气分子污染（AMC）和湿度的成分提供测试结果。 真空单元包括真空室，其构造成当成分的测试结果高于相应的阈值时将真空施加到容器上。

公开(公告)号：US09449864B2

公开(公告)日：2016-09-20

申请号：US14494621

申请日：2014-09-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Ming Lin ,  Wan-Lai Chen ,  Chia-Hung Huang ,  Chi-Ming Yang ,  Chin-Hsiang Lin

IPC: H01L21/683 ,  H01L21/68 ,  H01L21/268 ,  H01L23/544 ,  H01L21/67

CPC classification number: H01L21/681 ,  H01L21/268 ,  H01L21/67282 ,  H01L21/683 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A system for orienting a semiconductor wafer. The system includes a wafer retaining device configured to retain a semiconductor wafer, a light source configured to emit light toward an edge exclusion area of the wafer, and a lens configured to direct and focus light emitted from the light source at a subsurface first part of a first portion of the wafer to alter a crystalline structure of the subsurface first part and form a subsurface mark that is detectable using light of a predetermined wavelength, a predetermined transmittance through the wafer, and at a predetermined reflectance angle relative to an axis of rotation of the wafer and based on the predetermined wavelength.

Abstract translation: 一种用于定向半导体晶片的系统。 该系统包括被配置为保持半导体晶片的晶片保持装置，被配置为朝向晶片的边缘排除区域发光的光源，以及被配置为将来自光源的光从第一部分 晶片的第一部分，以改变地下第一部分的晶体结构，并形成可使用预定波长的光，通过晶片的预定透射率和相对于旋转轴线的预定反射角可检测的地下标记 并且基于预定波长。

公开(公告)号：US20150352686A1

公开(公告)日：2015-12-10

申请号：US14829995

申请日：2015-08-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiann Lih Wu ,  Chi-Ming Yang ,  James Jeng-Jyi Hwang

IPC: B24B49/04 ,  B24B37/013 ,  H01L21/67 ,  H01L21/306 ,  H01L21/66 ,  B24B37/015 ,  B24B49/14

CPC classification number: B24B49/04 ,  B24B37/013 ,  B24B37/015 ,  B24B37/042 ,  B24B37/105 ,  B24B49/105 ,  B24B49/14 ,  H01L21/30625 ,  H01L21/67075 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26

Abstract: A localized chemical mechanical polishing (CMP) platform is provided. A table is configured to support a workpiece with a to-be-polished surface. A polishing pad is spaced from the table with a width less than about half that of the table. The polishing pad is configured to individually polish rough regions of hillocks or valleys on the to-be-polished surface. A slurry distribution system is configured to apply slurry to an interface between the polishing pad and the workpiece. A cleaning system is configured to clean the workpiece in situ on the table. A drying system is configured to dry the workpiece in situ on the table. A method for CMP with local profile control and a system with local profile control are also provided.

Abstract translation: 提供了一种局部化学机械抛光（CMP）平台。 桌子被配置为支撑具有待抛光表面的工件。 抛光垫与桌子间隔开，宽度小于餐桌的一半。 抛光垫被配置为分别抛光被抛光表面上的小丘或谷的粗糙区域。 浆料分配系统被配置为将浆料施加到抛光垫和工件之间的界面。 清洁系统被配置为在工作台上原位清洁工件。 干燥系统构造成在工作台上原位干燥工件。 还提供了具有局部轮廓控制的CMP和具有局部轮廓控制的系统的方法。

公开(公告)号：US09023664B2

公开(公告)日：2015-05-05

申请号：US13777212

申请日：2013-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi-Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo-Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/67

CPC classification number: H01L22/20 ,  H01L21/67248 ,  H01L21/67253 ,  H01L22/12

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

Abstract translation: 提供了一种用于控制电路的关键尺寸（CD）的装置和方法。 一种装置包括控制器，用于在第一基板上的蚀刻膜中的电路图案的各个位置处接收CD测量值，以及用于在第二基板上形成膜材料的第二膜的单晶片室。 单个晶片室响应于来自控制器的信号，以基于测量的CD来局部地调整第二胶片的厚度。 一种方法提供了蚀刻第一衬底上的膜的电路图案，测量电路图案的CD，基于所测量的CD调整单晶片室以在第二半导体衬底上形成第二膜。 基于测量的CD来局部地调整第二膜厚度。

公开(公告)号：US20140158172A1

公开(公告)日：2014-06-12

申请号：US13706403

申请日：2012-12-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jyh-Shiou Hsu ,  Chi-Ming Yang ,  Kuo-Sheng Chuang

IPC: B08B9/46

CPC classification number: B08B9/46 ,  B08B9/0861 ,  H01L21/67051 ,  H01L21/67207 ,  H01L21/67253 ,  H01L21/67393

Abstract: A system for cleaning a container such as semiconductor wafer carrier includes a housing, a cleaning unit in the housing, an analyzing unit within the housing, and a vacuum unit within the housing. The cleaning unit comprises a cleaning chamber, and is configured to spray a cleaning medium into the container in the cleaning chamber and dry the container. The analyzing unit is configured to analyze air inside the container coming out of the cleaning chamber, and provide a testing result for each ingredient of possible airborne molecular contamination (AMC) and humidity. The vacuum unit comprises a vacuum chamber configured to apply vacuum onto a container when the testing result for an ingredient is higher than a respective threshold.

Abstract translation: 用于清洁诸如半导体晶片载体的容器的系统包括壳体，壳体中的清洁单元，壳体内的分析单元以及壳体内的真空单元。 清洁单元包括清洁室，并且构造成将清洁介质喷射到清洁室中的容器中并干燥容器。 分析单元被配置为分析来自清洁室的容器内的空气，并且为每种可能的空气分子污染（AMC）和湿度的成分提供测试结果。 真空单元包括真空室，其构造成当成分的测试结果高于相应的阈值时将真空施加到容器上。

公开(公告)号：US10269591B2

公开(公告)日：2019-04-23

申请号：US14061602

申请日：2013-10-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Ying-Hsueh Changchien ,  Yu-Ming Lee ,  Chi-Ming Yang

IPC: H01L21/311 ,  H01L21/67

Abstract: A method of selectively removing silicon nitride is provided. The method includes: providing a wafer having silicon nitride on a surface of the wafer; providing a mixture of phosphoric acid and a silicon-containing material; and delivering the mixture to the surface of the wafer to remove the silicon nitride. Single wafer etching apparatuses of selectively removing silicon nitride are also provided.

公开(公告)号：US10113233B2

公开(公告)日：2018-10-30

申请号：US14680105

申请日：2015-04-07

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Lin Chang ,  Hsin-Hsien Wu ,  Zin-Chang Wei ,  Chi-Ming Yang ,  Chyi Shyuan Chern ,  Jun-Lin Yeh ,  Jih-Jse Lin ,  Jo Fei Wang ,  Ming-Yu Fan ,  Jong-I Mou

IPC: C23C16/458 ,  C23C16/46 ,  H01J37/32 ,  H01L21/67 ,  G06F17/18 ,  G06Q30/00 ,  G06K9/62

Abstract: An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's.

公开(公告)号：US09859139B2

公开(公告)日：2018-01-02

申请号：US14798661

申请日：2015-07-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Nai-Han Cheng ,  Chi-Ming Yang

IPC: H01L21/67 ,  G01B11/16 ,  G01B11/14 ,  G01B11/24 ,  H01L21/66 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L21/67288 ,  G01B11/14 ,  G01B11/161 ,  G01B11/2441 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/20 ,  H01L23/562 ,  H01L24/11 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/1146 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/014

Abstract: The present disclosure relates to a method of bump metrology that relies upon advanced process control (APC) to provide substrate warpage parameters describing a warpage of a substrate to a bump metrology module to improve focus of the bump metrology module. In some embodiments, the method measures one or more substrate warpage parameters of a semiconductor substrate. An initial focal height of a lens of a bump metrology module is calculated based upon the measured substrate warpage parameters. The lens of the bump metrology module is then placed at the initial focal height, and height and critical dimensions of a plurality of bumps on the semiconductor substrate are subsequently measured using the lens. By providing the substrate warpage parameters to the bump metrology module, the bump metrology module can use real-time process control to account for wafer warpage, thereby improving throughput and yield.