公开(公告)号：US20170103954A1

公开(公告)日：2017-04-13

申请号：US15389738

申请日：2016-12-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/147 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/10135 ,  H01L2224/11464 ,  H01L2224/13012 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13582 ,  H01L2224/13644 ,  H01L2224/13664 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81007 ,  H01L2224/81139 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.

公开(公告)号：US20250046753A1

公开(公告)日：2025-02-06

申请号：US18363096

申请日：2023-08-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: A method of manufacturing a semiconductor device, the method includes bonding a first die and a second die to a first side of a wafer, wherein after bonding the first die and the second die to the first side of the wafer, a gap is disposed between the first die and the second die, wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap, depositing a third dielectric layer on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap, forming a molding material over the third dielectric layer to fill the gap, and performing a planarization process to expose top surfaces of the first die and the second die.

公开(公告)号：US20240297166A1

公开(公告)日：2024-09-05

申请号：US18664483

申请日：2024-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Sung-Hui Huang ,  Kuan-Yu Huang ,  Hsien-Pin Hu ,  Yushun Lin ,  Heh-Chang Huang ,  Hsing-Kuo Hsia ,  Chih-Chieh Hung ,  Ying-Ching Shih ,  Chin-Fu Kao ,  Wen-Hsin Wei ,  Li-Chung Kuo ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/24 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/4803 ,  H01L21/4853 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

公开(公告)号：US11967546B2

公开(公告)日：2024-04-23

申请号：US17870099

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shang-Yun Hou ,  Hsien-Pin Hu ,  Sao-Ling Chiu ,  Wen-Hsin Wei ,  Ping-Kang Huang ,  Chih-Ta Shen ,  Szu-Wei Lu ,  Ying-Ching Shih ,  Wen-Chih Chiou ,  Chi-Hsi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49861 ,  H01L24/13 ,  H01L23/5385 ,  H01L2224/023 ,  H01L2225/107

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

公开(公告)号：US20240071849A1

公开(公告)日：2024-02-29

申请号：US17822476

申请日：2022-08-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jian-You Chen ,  Kuan-Yu Huang ,  Li-Chung Kuo ,  Chen-Hsuan Tsai ,  Kung-Chen Yeh ,  Hsien-Ju Tsou ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/16 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package including one or more dam structures and the method of forming are provided. A semiconductor package may include an interposer, a semiconductor die bonded to a first side of the interposer, an encapsulant on the first side of the interposer encircling the semiconductor die, a substrate bonded to the a second side of the interposer, an underfill between the interposer and the substrate, and one or more of dam structures on the substrate. The one or more dam structures may be disposed adjacent respective corners of the interposer and may be in direct contact with the underfill. The coefficient of thermal expansion of the one or more of dam structures may be smaller than the coefficient of thermal expansion of the underfill.

公开(公告)号：US11842936B2

公开(公告)日：2023-12-12

申请号：US17384923

申请日：2021-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/0652

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US11824040B2

公开(公告)日：2023-11-21

申请号：US16805865

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

公开(公告)号：US20230253280A1

公开(公告)日：2023-08-10

申请号：US18194876

申请日：2023-04-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yu-Wei Chen ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee ,  Kuan-Yu Huang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/3135 ,  H01L23/3128 ,  H01L23/49816 ,  H01L21/563 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/0651 ,  H01L2225/0652

Abstract: A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.

公开(公告)号：US20220199465A1

公开(公告)日：2022-06-23

申请号：US17676627

申请日：2022-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Ying-Ching Shih ,  Szu-Wei Lu ,  Jing-Cheng Lin ,  Long Hua Lee

IPC: H01L21/768 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

Abstract: A method of forming a semiconductor device includes attaching a metal foil to a carrier, the metal foil being pre-made prior to attaching the metal foil; forming a conductive pillar on a first side of the metal foil distal the carrier; attaching a semiconductor die to the first side of the metal foil; forming a molding material around the semiconductor die and the conductive pillar; and forming a redistribution structure over the molding material.

公开(公告)号：US11289424B2

公开(公告)日：2022-03-29

申请号：US16655260

申请日：2019-10-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Wei Wu ,  Chen-Hua Yu ,  Kuo-Chung Yee ,  Szu-Wei Lu ,  Ying-Ching Shih

IPC: H01L23/495 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065

Abstract: Provided are a package and a method of manufacturing the same. The package includes a first die, a second die, a bridge structure, an encapsulant, and a redistribution layer (RDL) structure. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die to electrically connect the first die and the second die. The encapsulant laterally encapsulates the first die, the second die, and the bridge structure. The RDL structure is disposed over a backside of the bridge structure and the encapsulant. The RDL structure includes an insulating structure and a conductive pattern, the conductive pattern is disposed over the insulating structure and extending through the insulating structure and a substrate of the bridge structure, so as to form at least one through via in the substrate of the bridge structure.