公开(公告)号：US20160064300A1

公开(公告)日：2016-03-03

申请号：US14521893

申请日：2014-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Kuo-Ming Chen

IPC: H01L23/34 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L24/14 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Abstract translation: 提供扇形晶圆级封装。 扇形晶片级封装包括半导体元件，模塑料，第一扇出结构，导热散热器和多个焊球。 半导体元件包括多个接合焊盘。 模塑料覆盖半导体元件。 第一扇出结构形成在半导体元件上，其中第一扇出结构具有电连接到接合焊盘的多个扇出接点。 导电散热器形成在第一扇出结构上，其中导电散热器具有填充有导电材料的多个通孔。 焊球形成在导电散热器上，其中焊球通过填充有导电材料的通孔与第一扇出结构电连接。

公开(公告)号：US09269645B1

公开(公告)日：2016-02-23

申请号：US14521893

申请日：2014-10-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chu-Fu Lin ,  Chien-Li Kuo ,  Kuo-Ming Chen

IPC: H01L23/40 ,  H01L23/34 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L24/14 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/105 ,  H01L2023/4037 ,  H01L2023/4043 ,  H01L2023/405 ,  H01L2023/4062 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/014 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043

Abstract: A fan-out wafer level package is provided. The fan-out wafer level package includes a semiconductor element, a molding compound, a first fan-out structure, a conductive heat spreader, and a plurality of solder balls. The semiconductor element includes a plurality of bonding pads. The molding compound covers the semiconductor element. The first fan-out structure is formed on the semiconductor element, wherein the first fan-out structure has a plurality of fan-out contacts electrically connected to the bonding pads. The conductive heat spreader is formed on the first fan-out structure, wherein the conductive heat spreader has a plurality of through holes filled with a conductive material. The solder balls are formed on the conductive heat spreader, wherein the solder balls are electrically connected to the first fan-out structure via the through holes filled with the conductive material.

Abstract translation: 提供扇形晶圆级封装。 扇形晶片级封装包括半导体元件，模塑料，第一扇出结构，导热散热器和多个焊球。 半导体元件包括多个接合焊盘。 模塑料覆盖半导体元件。 第一扇出结构形成在半导体元件上，其中第一扇出结构具有电连接到接合焊盘的多个扇出接点。 导电散热器形成在第一扇出结构上，其中导电散热器具有填充有导电材料的多个通孔。 焊球形成在导电散热器上，其中焊球通过填充有导电材料的通孔与第一扇出结构电连接。

公开(公告)号：US20150364532A1

公开(公告)日：2015-12-17

申请号：US14341848

申请日：2014-07-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/481 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inductor formed on a semiconductor substrate includes a semiconductor substrate, an inductor structure formed on the semiconductor substrate, and a plurality of slice structures formed in the semiconductor substrate. An extending direction of the slice structures is perpendicular to a surface of the semiconductor substrate. The slice structures are overlapped by the inductor.

Abstract translation: 形成在半导体衬底上的电感器包括半导体衬底，形成在半导体衬底上的电感结构以及形成在半导体衬底中的多个片结构。 切片结构的延伸方向垂直于半导体衬底的表面。 切片结构由电感器重叠。

公开(公告)号：US20150303108A1

公开(公告)日：2015-10-22

申请号：US14716889

申请日：2015-05-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L21/76898 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/28026 ,  H01L21/31111 ,  H01L21/76224 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76877 ,  H01L2224/05009 ,  H01L2224/0557 ,  H01L2224/06181

Abstract: A semiconductor device includes a substrate with a front side and a back side, an ILD, disposed on the substrate, a cap layer disposed on the backside of the substrate, a TSV penetrating the cap layer, the substrate and the ILD, wherein a cap layer sidewall in the TSV juts out beyond the substrate sidewall the TSV with a predetermined distance, and a liner is disposed on the substrate sidewall, wherein the liner partially overlaps with the cap layer.

Abstract translation: 一种半导体器件包括具有正面和背面的衬底，设置在衬底上的ILD，设置在衬底背面上的覆盖层，穿透覆盖层，衬底和ILD的TSV，其中帽 TSV中的层侧壁突出超过基板侧壁具有预定距离的TSV，并且衬垫设置在衬底侧壁上，其中衬垫部分地与盖层重叠。

公开(公告)号：US20150279829A1

公开(公告)日：2015-10-01

申请号：US14226802

申请日：2014-03-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L21/311 ,  H01L25/065 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/561 ,  H01L24/19 ,  H01L24/24 ,  H01L24/82 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/80896 ,  H01L2224/81895 ,  H01L2224/8203 ,  H01L2224/92124 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/15311 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/82 ,  H01L2924/00

Abstract: A wafer package process includes the following steps. A wafer with a plurality of first dies is provided. A plurality of second dies are bonded on the first dies by using flip chip technology, wherein the size of the first die is larger than that of the second die. A molding material is formed to entirely cover the second dies and the wafer. A through via is formed in the molding material. A conductive material is formed to fill the through via onto the molding material.

Abstract translation: 晶片封装工艺包括以下步骤。 提供具有多个第一管芯的晶片。 通过使用倒装芯片技术将多个第二管芯结合在第一管芯上，其中第一管芯的尺寸大于第二管芯的尺寸。 成型材料形成为完全覆盖第二模具和晶片。 在模制材料中形成通孔。 形成导电材料以将通孔填充到模制材料上。

公开(公告)号：US20150179516A1

公开(公告)日：2015-06-25

申请号：US14140523

申请日：2013-12-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin ,  Chien-Li Kuo

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76846 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/02 ,  H01L2224/023 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/02315 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/05548 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for fabricating integrated structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon hole in the substrate; forming a patterned resist on the substrate, wherein the patterned resist comprises at least one opening corresponding to a redistribution layer (RDL) pattern and exposing the through-silicon hole and at least another opening corresponding to another redistribution layer (RDL) pattern and connecting to the at least one opening; and forming a conductive layer to fill the through-silicon hole, the at least one opening and the at least another opening in the patterned resist so as to form a through-silicon via, a through-silicon via RDL pattern and another RDL pattern in one structure.

Abstract translation: 公开了一种制造一体化结构的方法。 该方法包括以下步骤：提供衬底; 在所述基板中形成贯通硅孔; 在衬底上形成图案化的抗蚀剂，其中所述图案化抗蚀剂包括对应于再分布层（RDL）图案的至少一个开口，并暴露所述穿硅孔和至少另一个对应于另一再分布层（RDL）图案的开口，并连接到 所述至少一个开口; 以及形成导电层以填充图案化的抗蚀剂中的通孔，至少一个开口和至少另一个开口，以便形成贯穿硅通孔，穿硅通孔RDL图案和另一RDL图案 一个结构。

公开(公告)号：US20140346645A1

公开(公告)日：2014-11-27

申请号：US13900565

申请日：2013-05-23

Applicant: United Microelectronics Corp.

Inventor： Chien-Li Kuo ,  Chun-Hung Chen ,  Ming-Tse Lin ,  Yung-Chang Lin

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through silicon via includes a substrate and a conductive plug. The substrate has a hole in a side. The conductive plug is disposed in the hole, and the conductive plug having an upper part protruding from the side, wherein the upper part has a top part and a bottom part, and the top part is finer than the bottom part. Moreover, a through silicon via process formed said through silicon via is also provided, which includes the following step. A hole is formed in a substrate from a side. A first conductive material is formed to cover the hole and the side. A patterned photoresist is formed to cover the side but exposing the hole. A second conductive material is formed on the exposed first conductive material. The patterned photoresist is removed. The first conductive material on the side is removed to form a conductive plug in the hole.

Abstract translation: 透硅通孔包括基底和导电塞。 基板在一侧具有孔。 导电插头设置在孔中，导电插头具有从侧面突出的上部，其中上部具有顶部和底部，并且顶部比底部更细。 此外，还提供了通过硅通孔形成的贯穿硅通孔工艺，其包括以下步骤。 从一侧在基板上形成孔。 形成第一导电材料以覆盖孔和侧面。 形成图案化的光致抗蚀剂以覆盖侧面但暴露孔。 在暴露的第一导电材料上形成第二导电材料。 去除图案化的光致抗蚀剂。 去除侧面上的第一导电材料以在孔中形成导电塞。

公开(公告)号：US20140332952A1

公开(公告)日：2014-11-13

申请号：US13890397

申请日：2013-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo ,  Yung-Chang Lin ,  Chun-Ting Yeh ,  Kuei-Sheng Wu

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L23/481 ,  H01L22/14 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure comprising a substrate, a dielectric layer, a conductor post, a first conductive layer structure and a second conductive layer structure is provided. The substrate comprises an opening structure. The dielectric layer is disposed on a sidewall of the opening structure. The conductor structure is disposed in the opening structure and covers the dielectric layer. The first and second conductive layer structures are electrically connected to the conductor post. A voltage difference is existed between the first and second conductive layer structures, such that a current is passing through the first conductive layer structure, the opening structure and second conductive layer structure. A resistance values is related to the voltage difference and the current. A dimension of the opening structure is 10 times greater than a dimension of the first and second conductive layer structures.

Abstract translation: 提供了包括基板，电介质层，导体柱，第一导电层结构和第二导电层结构的半导体结构。 基板包括开口结构。 电介质层设置在开口结构的侧壁上。 导体结构设置在开口结构中并覆盖电介质层。 第一和第二导电层结构电连接到导体柱。 在第一和第二导电层结构之间存在电压差，使得电流通过第一导电层结构，开口结构和第二导电层结构。 电阻值与电压差和电流有关。 开口结构的尺寸是第一和第二导电层结构的尺寸的10倍。

公开(公告)号：US20140203394A1

公开(公告)日：2014-07-24

申请号：US13747492

申请日：2013-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Tse Lin ,  Chu-Fu Lin ,  Chien-Li Kuo ,  Yung-Chang Lin

IPC: H01L23/538

CPC classification number: H01L21/76898 ,  H01L21/283 ,  H01L21/302 ,  H01L21/7685 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76883 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/16 ,  H01L28/60 ,  H01L2224/02317 ,  H01L2224/0401 ,  H01L2224/4824 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a method of forming a chip with TSV electrode. A substrate with a first surface and a second surface is provided. A thinning process is performed from a side of the second surface so the second surface becomes a third surface. Next, a penetration via which penetrates through the first surface and the third surface is formed in the substrate. A patterned material layer is formed on the substrate, wherein the patterned material layer has an opening exposes the penetration via. A conductive layer is formed on the third surface thereby simultaneously forming a TSV electrode in the penetration via and a surface conductive layer in the opening.

Abstract translation: 本发明提供一种用TSV电极形成芯片的方法。 提供具有第一表面和第二表面的基底。 从第二表面的一侧进行变薄处理，使得第二表面变成第三表面。 接下来，在衬底中形成穿过第一表面和第三表面的穿透。 图案化材料层形成在衬底上，其中图案化材料层具有开口以暴露穿透通孔。 导电层形成在第三表面上，从而同时在穿透孔中形成TSV电极和开口中的表面导电层。

公开(公告)号：US10861832B2

公开(公告)日：2020-12-08

申请号：US16889828

申请日：2020-06-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Li Kuo

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/78 ,  H01L23/00 ,  H01L21/56 ,  H01L25/18 ,  H01L23/31

Abstract: The present invention provides a method of manufacturing a package structure. An array chip including a plurality of first dies is provided. A wafer including a plurality of second dies is provided. A package step is carried out to package the array chip onto the wafer so as to electrically connect the first die and the second die. The present invention further provides a semiconductor wafer and a package structure.