公开(公告)号：US20100187555A1

公开(公告)日：2010-07-29

申请号：US12752977

申请日：2010-04-01

Applicant: Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L33/00

CPC classification number: H01L33/22 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/32 ,  H01S5/0215 ,  H01S5/0421 ,  H01S5/18347 ,  H01S5/18369 ,  H01S5/1838 ,  H01S5/32341

Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Abstract translation: An（Al，Ga，In）N和ZnO直接晶圆键合发光二极管（LED），其中光通过导电ZnO。 为（Al，Ga，In）N和ZnO晶圆制备平坦且干净的表面。 然后在（Al，Ga，In）N和ZnO晶片之间进行晶片接合工艺，其中（Al，Ga，In）N和ZnO晶片被接合在一起，然后在氮气氛下在单轴压力下在 设定温度一段时间。 在晶片接合工艺之后，ZnO被成形为用于从LED内部增加光提取。

公开(公告)号：US07728356B2

公开(公告)日：2010-06-01

申请号：US12131704

申请日：2008-06-02

Applicant: Chang Soo Suh ,  Umesh K. Mishra

Inventor： Chang Soo Suh ,  Umesh K. Mishra

IPC: H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/432 ,  H01L29/66462

Abstract: An enhancement mode High Electron Mobility Transistor (HEMT) comprising a p-type nitride layer between the gate and a channel of the HEMT, for reducing an electron population under the gate. The HEMT may also comprise an Aluminum Nitride (AlN) layer between an AlGaN layer and buffer layer of the HEMT to reduce an on resistance of a channel.

Abstract translation: 一种增强型高电子迁移率晶体管（HEMT），其包括在HEMT的栅极和沟道之间的p型氮化物层，用于减少栅极下的电子群。 HEMT还可以在AlGaN层和HEMT的缓冲层之间包含氮化铝（AlN）层，以降低通道的导通电阻。

公开(公告)号：US07719020B2

公开(公告)日：2010-05-18

申请号：US11454691

申请日：2006-06-16

Applicant: Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Akihiko Murai ,  Christina Ye Chen ,  Daniel B. Thompson ,  Lee S. McCarthy ,  Steven P. DenBaars ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L29/22 ,  H01L29/04

CPC classification number: H01L33/22 ,  H01L33/0079 ,  H01L33/20 ,  H01L33/32 ,  H01S5/0215 ,  H01S5/0421 ,  H01S5/18347 ,  H01S5/18369 ,  H01S5/1838 ,  H01S5/32341

Abstract: An (Al, Ga, In)N and ZnO direct wafer bonded light emitting diode (LED), wherein light passes through electrically conductive ZnO. Flat and clean surfaces are prepared for both the (Al, Ga, In)N and ZnO wafers. A wafer bonding process is then performed between the (Al, Ga, In)N and ZnO wafers, wherein the (Al, Ga, In)N and ZnO wafers are joined together and then wafer bonded in a nitrogen ambient under uniaxial pressure at a set temperature for a set duration. After the wafer bonding process, ZnO is shaped for increasing light extraction from inside of LED.

Abstract translation: An（Al，Ga，In）N和ZnO直接晶圆键合发光二极管（LED），其中光通过导电ZnO。 为（Al，Ga，In）N和ZnO晶圆制备平坦且干净的表面。 然后在（Al，Ga，In）N和ZnO晶片之间进行晶片接合工艺，其中（Al，Ga，In）N和ZnO晶片被接合在一起，然后在氮气氛下在单轴压力下在 设定温度一段时间。 在晶片接合工艺之后，ZnO被成形为用于从LED内部增加光提取。

公开(公告)号：US20080296617A1

公开(公告)日：2008-12-04

申请号：US12113847

申请日：2008-05-01

Applicant: Umesh K. Mishra ,  Lee S. McCarthy

Inventor： Umesh K. Mishra ,  Lee S. McCarthy

IPC: H01L29/778 ,  H01L21/30 ,  H01L29/737

CPC classification number: H01L29/7802 ,  H01L21/187 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/7371 ,  H01L29/7786

Abstract: A method for fabricating an electronic device, comprising wafer bonding a first semiconductor material to a III-nitride semiconductor, at a temperature below 550° C., to form a device quality heterojunction between the first semiconductor material and the III-nitride semiconductor, wherein the first semiconductor material is different from the III-nitride semiconductor and is selected for superior properties, or preferred integration or fabrication characteristics in the injector region as compared to the III-nitride semiconductor.

Abstract translation: 一种制造电子器件的方法，包括在低于550℃的温度下将第一半导体材料晶体结合到III族氮化物半导体，以在第一半导体材料和III族氮化物半导体之间形成器件质量异质结，其中 第一半导体材料与III族氮化物半导体不同，并且与III族氮化物半导体相比被选择用于喷射器区域中的优异性能或优选的集成或制造特性。

公开(公告)号：US07354782B2

公开(公告)日：2008-04-08

申请号：US10916819

申请日：2004-08-11

Applicant: Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

Inventor： Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

IPC: H01L21/00

CPC classification number: H05K1/0206 ,  H01L21/8252 ,  H01L23/147 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/66 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/7787 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/73253 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/30105 ,  H05K1/181 ,  H05K2201/066 ,  Y10T29/4913 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A flip-chip integrated circuit and method for fabricating the integrated circuit are disclosed. A method according to the invention comprises forming a plurality of active semiconductor devices on a wafer and separating the active semiconductor devices. Passive components and interconnections are formed on a surface of a circuit substrate and at least one conductive via is formed through the circuit substrate. At least one of the active semiconductor devices is flip-chip mounted on the circuit substrate with at least one of the bonding pads in electrical contact with one of the conductive vias. A flip-chip integrated circuit according to the present invention comprises a circuit substrate having passive components and interconnections on one surface and can have a conductive via through it. An active semiconductor device is flip-chip mounted on the circuit substrate, one of the at least one vias is in contact with one of the at least one the device's terminals. The present invention is particularly applicable to Group III nitride based active semiconductor devices grown on SiC substrates. The passive components and interconnects can then be formed on a lower cost, higher diameter wafer made of GaAs or Si. After separation, the Group III devices can be flip-chip mounted on the GaAs or Si substrate.

Abstract translation: 公开了一种用于制造集成电路的倒装芯片集成电路和方法。 根据本发明的方法包括在晶片上形成多个有源半导体器件并分离有源半导体器件。 无源元件和互连形成在电路基板的表面上，并且通过电路基板形成至少一个导电通孔。 至少一个有源半导体器件被倒装芯片安装在电路基板上，其中至少一个接合焊盘与导电通孔之一电接触。 根据本发明的倒装芯片集成电路包括在一个表面上具有无源部件和互连的电路基板，并且可以具有通过其的导电通孔。 有源半导体器件被倒装安装在电路基板上，所述至少一个通孔中的一个与该器件的至少一个端子中的一个接触。 本发明特别适用于在SiC衬底上生长的III族氮化物基有源半导体器件。 然后可以在GaAs或Si制成的较低成本，更高直径的晶圆上形成无源部件和互连。 分离后，III组器件可以倒装安装在GaAs或Si衬底上。

公开(公告)号：US09496353B2

公开(公告)日：2016-11-15

申请号：US12898341

申请日：2010-10-05

Applicant: Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

Inventor： Alessandro Chini ,  Umesh K. Mishra ,  Primit Parikh ,  Yifeng Wu

IPC: H01L29/40 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/207 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/404 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/401 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/42312 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/785

Abstract: A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.

Abstract translation: 使用在场效应晶体管的表面上的介电材料沉积/生长，介电材料蚀刻和金属蒸发的连续步骤来制造单栅极或多栅极场板的工艺。 这种制造工艺允许对场板操作的严格控制，因为介电材料沉积/生长通常是良好可控的工艺。 此外，沉积在器件表面上的电介质材料不需要从器件本征区域去除：这基本上使得能够实现电镀设备，而不需要低损耗介电材料干/湿蚀刻。 使用多个栅极场板还通过多个连接降低栅极电阻，从而提高大的周边和/或亚微米栅极器件的性能。

公开(公告)号：US09129977B2

公开(公告)日：2015-09-08

申请号：US13306763

申请日：2011-11-29

Applicant: Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

Inventor： Hugues Marchand ,  Brendan J. Moran ,  Umesh K. Mishra ,  James S. Speck

IPC: H01L33/32 ,  H01L29/267 ,  H01L23/00 ,  C30B25/02 ,  C30B29/40 ,  H01L21/02 ,  H01L33/00 ,  H01L29/20 ,  H01L29/205 ,  H01L33/12

CPC classification number: H01L23/562 ,  C30B25/02 ,  C30B29/403 ,  C30B29/406 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0251 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/205 ,  H01L33/0025 ,  H01L33/0066 ,  H01L33/0075 ,  H01L33/12 ,  H01L33/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of controlling stress in GaN films deposited on silicon and silicon carbide substrates and the films produced therefrom are disclosed. A typical method comprises providing a substrate and depositing a graded gallium nitride layer on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply. A typical semiconductor film comprises a substrate and a graded gallium nitride layer deposited on the substrate having a varying composition of a substantially continuous grade from an initial composition to a final composition formed from a supply of at least one precursor in a growth chamber without any interruption in the supply.

Abstract translation: 公开了控制沉积在硅和碳化硅衬底上的GaN膜中的应力控制方法和由其制备的膜。 典型的方法包括提供衬底并在衬底上沉积梯度的氮化镓层，其具有基本上连续等级的从初始组成到由生长室中的至少一种前体的供应形成的最终组成的变化的组成，而不会中断 在供应。 典型的半导体膜包括沉积在衬底上的衬底和梯度的氮化镓层，其具有从初始组成到最终组成的基本连续等级的变化的组成，其由在生长室中供应至少一种前体而形成，而不会中断 在供应。

公开(公告)号：US08324637B2

公开(公告)日：2012-12-04

申请号：US12782107

申请日：2010-05-18

Applicant: James P. Ibbetson ,  Bernd P. Keller ,  Umesh K. Mishra

Inventor： James P. Ibbetson ,  Bernd P. Keller ,  Umesh K. Mishra

IPC: H01L27/15

CPC classification number: H01L33/04 ,  H01L33/0016 ,  H01L33/08 ,  H01L33/32

Abstract: An LED made from a wide band gap semiconductor material and having a low resistance p-type confinement layer with a tunnel junction in a wide band gap semiconductor device is disclosed. A dissimilar material is placed at the tunnel junction where the material generates a natural dipole. This natural dipole is used to form a junction having a tunnel width that is smaller than such a width would be without the dissimilar material. A low resistance p-type confinement layer having a tunnel junction in a wide band gap semiconductor device may be fabricated by generating a polarization charge in the junction of the confinement layer, and forming a tunnel width in the junction that is smaller than the width would be without the polarization charge. Tunneling through the tunnel junction in the confinement layer may be enhanced by the addition of impurities within the junction. These impurities may form band gap states in the junction.

Abstract translation: 公开了一种由宽带隙半导体材料制成的LED，并具有在宽带隙半导体器件中具有隧道结的低电阻p型约束层。 不同的材料放置在材料产生天然偶极子的隧道结处。 该天然偶极子用于形成隧道宽度小于不具有不同材料的宽度的接合点。 在宽带隙半导体器件中具有隧道结的低电阻p型限制层可以通过在限制层的接合处产生极化电荷并在接合部中形成小于宽度的隧道宽度来制造 没有极化电荷。 可以通过在连接处添加杂质来增强通过限制层中的隧道结的隧穿。 这些杂质可能在结中形成带隙状态。

公开(公告)号：US08193020B2

公开(公告)日：2012-06-05

申请号：US12466705

申请日：2009-05-15

Applicant: Stacia Keller ,  Umesh K. Mishra ,  Nicholas K. Fichtenbaum

Inventor： Stacia Keller ,  Umesh K. Mishra ,  Nicholas K. Fichtenbaum

IPC: H01L21/20

CPC classification number: C30B25/02 ,  C30B29/403 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02538 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262

Abstract: Methods for the heteroepitaxial growth of smooth, high quality films of N-face GaN film grown by MOCVD are disclosed. Use of a misoriented substrate and possibly nitridizing the substrate allow for the growth of smooth N-face GaN and other Group III nitride films as disclosed herein. The present invention also avoids the typical large (μm sized) hexagonal features which make N-face GaN material unacceptable for device applications. The present invention allows for the growth of smooth, high quality films which makes the development of N-face devices possible.

Abstract translation: 公开了通过MOCVD生长的N面GaN薄膜的平滑，高质量薄膜异质外延生长的方法。 使用错误取向的衬底并且可能使衬底氮化使得能够生长平滑的N面GaN和其他III族氮化物膜，如本文所公开的。 本发明还避免了典型的大（μm尺寸）六边形特征，这使得N面GaN材料不适合于器件应用。 本发明允许平滑，高质量的膜的生长，这使得N面装置的发展成为可能。

公开(公告)号：US08188458B2

公开(公告)日：2012-05-29

申请号：US13099834

申请日：2011-05-03

Applicant: Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James S. Speck ,  Shuji Nakamura ,  Umesh K. Mishra

Inventor： Michael D. Craven ,  Stacia Keller ,  Steven P. DenBaars ,  Tal Margalith ,  James S. Speck ,  Shuji Nakamura ,  Umesh K. Mishra

IPC: H01L29/15

CPC classification number: C30B29/403 ,  C30B25/02 ,  C30B25/04 ,  C30B25/105 ,  C30B25/18 ,  C30B29/406 ,  C30B29/605 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647

Abstract: A method for forming non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices. Non-polar (11 20) a-plane GaN layers are grown on an r-plane (1 102) sapphire substrate using MOCVD. These non-polar (11 20) a-plane GaN layers comprise templates for producing non-polar (Al,B,In,Ga)N quantum well and heterostructure materials and devices.

Abstract translation: 一种形成非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的方法。 使用MOCVD在非平面（1120）蓝宝石衬底上生长非极性（11 20）a面GaN层。 这些非极性（11 20）a面GaN层包括用于产生非极性（Al，B，In，Ga）N量子阱和异质结构材料和器件的模板。