公开(公告)号：US07939907B2

公开(公告)日：2011-05-10

申请号：US11755045

申请日：2007-05-30

申请人： Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

发明人： Hideki Osaka ,  Yutaka Uematsu ,  Eiichi Suzuki

IPC分类号： H01L29/00 ,  H01L23/52

CPC分类号： H05K1/0236 ,  H01L23/66 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09681 ,  H05K2201/09727 ,  H05K2201/09972 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： High density mounting and power source sharing are achieved by a digital semiconductor element and an analog semiconductor element provided in a common semiconductor device. A power layer for analog operation is connected to one end of an EBG (Electromagnetic Band Gap) layer, a power layer for digital operation is connected to the other end of the EBG layer, ground terminals for the respective elements are connected to a common ground layer, and a ground layer for separating the power layer for analog operation and the EBG layer from each other is disposed between the power layer for analog operation and the EBG layer. Thereby, high density mounting is achieved along with reducing interference of the power source to an analog chip.

摘要翻译： 通过设置在公共半导体器件中的数字半导体元件和模拟半导体元件来实现高密度安装和电源共享。 用于模拟操作的功率层连接到EBG（电磁带隙）层的一端，用于数字操作的功率层连接到EBG层的另一端，各个元件的接地端子连接到公共地 层和用于模拟操作的功率层和EBG层之间分离的接地层设置在用于模拟操作的功率层和EBG层之间。 从而，实现了高密度安装，同时减少了电源对模拟芯片的干扰。

公开(公告)号：US07768867B2

公开(公告)日：2010-08-03

申请号：US11761470

申请日：2007-06-12

申请人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

发明人： Yoji Nishio ,  Yutaka Uematsu ,  Seiji Funaba ,  Hideki Osaka ,  Tsutomu Hara ,  Koichiro Aoki

IPC分类号： G11C8/00

CPC分类号： G11C7/02 ,  G11C5/02 ,  G11C5/04 ,  H01L25/105 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： Stacked semiconductor device includes plural memory chips, stacked together, in which waveform distortion at high speed transmission is removed. Stacked semiconductor device 1 includes plural memory chips 11, 12 stacked together. Data strobe signal (DQS) and inverted data strobe signal (/DQS), as control signals for inputting/outputting data twice per cycle, are used as two single-ended data strobe signals. Data strobe signal and inverted data strobe signal mate with each other. Data strobe signal line for the data strobe signal L4 is connected to data strobe signal (DQS) pad of first memory chip 11. Inverted data strobe signal line for /DQS signal L5 is connected to inverted data strobe signal (/DQS) pad of second memory chip 12.

摘要翻译： 叠层半导体器件包括多个存储器芯片，堆叠在一起，其中高速传输中的波形失真被去除。 堆叠半导体器件1包括堆叠在一起的多个存储器芯片11,12。 作为用于每周期两次输入/输出数据的控制信号的数据选通信号（DQS）和反相数据选通信号（/ DQS）被用作两个单端数据选通信号。 数据选通信号和反相数据选通信号相互配合。 用于数据选通信号L4的数据选通信号线连接到第一存储芯片11的数据选通信号（DQS）焊盘。用于/ DQS信号L5的反相数据选通信号线连接到第二存储芯片11的反相数据选通信号（/ DQS）焊盘 存储芯片12。

公开(公告)号：US20100013528A1

公开(公告)日：2010-01-21

申请号：US12504319

申请日：2009-07-16

申请人： Yutaka Uematsu ,  Tatsuya Saito ,  Yoji Nishio ,  Yukitoshi Hirose

发明人： Yutaka Uematsu ,  Tatsuya Saito ,  Yoji Nishio ,  Yukitoshi Hirose

IPC分类号： H03L5/00

CPC分类号： G11C11/406 ,  G11C11/40618 ,  G11C11/4074 ,  G11C2211/4067

摘要： A semiconductor device or an information processing system comprises a plurality of circuit units, and a control unit for controlling a start timing of large-current operations executed by the respective circuit units within a predetermined period, where the large-current operation involves a relatively large current which flows in a power supply system, as compared with other operations. The control unit controls the start timing of the large-current operation from one circuit unit to another such that the waveform of a current flowing from the power supply system is shaped into the waveform of a half cycle of a sinusoidal wave when the circuit units execute large-current operations within the predetermined period.

摘要翻译： 半导体器件或信息处理系统包括多个电路单元，以及控制单元，用于在预定时间段内控制由各个电路单元执行的大电流操作的开始定时，其中大电流操作涉及相对大的 与其他操作相比，在电源系统中流动的电流。 控制单元控制从一个电路单元到另一个电路单元的大电流操作的开始定时，使得当电路单元执行时，从电源系统流过的电流的波形被成形为正弦波的半周期的波形 在预定时段内的大电流操作。

公开(公告)号：US20080290495A1

公开(公告)日：2008-11-27

申请号：US12068606

申请日：2008-02-08

申请人： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

发明人： Yutaka Uematsu ,  Tatsuya Saito ,  Hideki Osaka ,  Yoji Nishio ,  Shunichi Saito

IPC分类号： H01L23/528

CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/09 ,  H05K1/111 ,  H05K1/167 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10636 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00

摘要： As a power feed route in a semiconductor chip, a power feed route which reduces antiresonance impedance in the frequency range of tens of MHz is to be realized thereby to suppress power noise in a semiconductor device. By inserting structures which raise the resistance in the medium frequency band into parts where the resistance is intrinsically high, such as power wiring in a semiconductor package and capacitor interconnecting electrode parts, the antiresonance impedance in the medium frequency band can be effectively reduced while keeping the impedance low at the low frequency.

摘要翻译： 作为半导体芯片中的馈电路径，可以实现降低数十MHz频率范围内的反谐振阻抗的馈电路径，从而抑制半导体器件的功率噪声。 通过插入将中频带中的电阻提升到电阻本身较高的部分的结构，例如半导体封装中的功率布线和电容器互连电极部件，可以有效地减少中频带中的反谐振阻抗，同时保持 阻抗低在低频。

公开(公告)号：US07187069B2

公开(公告)日：2007-03-06

申请号：US10981676

申请日：2004-11-05

申请人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

发明人： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Yukitoshi Hirose

IPC分类号： H01L23/02 ,  H01L23/34

CPC分类号： H01L23/642 ,  H01L23/5223 ,  H01L23/5228 ,  H01L23/5286 ,  H01L23/647 ,  H01L25/105 ,  H01L2224/73204 ,  H01L2924/19105 ,  H01L2924/3011

摘要： The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

摘要翻译： 本发明提供一种技术，其不会引起两个问题，即（1）增加电源/接地引脚的数量和（2）增加的馈电线电感，防止在控制电路中引起问题的噪声变为布线 并引入输出缓冲区。 更具体地，可以通过以下两种方法之一来实现上述：（A）为控制电路提供片上旁路电容器，并将控制电路的馈电路径与AC类似的输出缓冲器的馈电路径隔离 方式或（B）设计电参数（插入电阻），使得引入馈电路径的任何电参数噪声的振荡模式将变为过阻尼。

公开(公告)号：US20070047354A1

公开(公告)日：2007-03-01

申请号：US11511262

申请日：2006-08-29

申请人： Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

发明人： Yoji Nishio ,  Seiji Funaba ,  Yutaka Uematsu ,  Hideki Osaka

IPC分类号： G11C7/02

CPC分类号： G11C5/147 ,  G11C5/02 ,  G11C7/02 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4847 ,  H01L2924/00014 ,  H01L2924/10161 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

摘要翻译： 半导体模块包括第一半导体器件，第二半导体器件和参考电压提供电路。 第一半导体器件包括第一电极。 第二半导体器件包括第二电极。 参考电压提供电路用于向第一电极和第二电极提供参考电位，并用于抑制在第一电极和第二电极之间传递的噪声。

公开(公告)号：US20050153828A1

公开(公告)日：2005-07-14

申请号：US10508551

申请日：2003-03-28

申请人： Taiji Uekusa ,  Teruo Nakada ,  Kazuhiro Enoki ,  Yutaka Uematsu ,  Tetsuya Fujita ,  Yousuke Tanaka ,  Jin Yokoyama ,  Hiromi Shibuya

发明人： Taiji Uekusa ,  Teruo Nakada ,  Kazuhiro Enoki ,  Yutaka Uematsu ,  Tetsuya Fujita ,  Yousuke Tanaka ,  Jin Yokoyama ,  Hiromi Shibuya

IPC分类号： F02D43/00 ,  B01D53/94 ,  F01N3/02 ,  F01N3/022 ,  F01N3/023 ,  F01N3/035 ,  F01N3/08 ,  F01N3/20 ,  F01N3/22 ,  F01N3/24 ,  F01N3/28 ,  F01N3/30 ,  F01N11/00 ,  F01N13/02 ,  F02B29/04 ,  F02B37/00 ,  F02B37/16 ,  F02D41/04 ,  F02D45/00 ,  F02M25/07 ,  B01J29/04

CPC分类号： F02B37/164 ,  F01N3/023 ,  F01N3/035 ,  F01N3/0821 ,  F01N3/0885 ,  F01N3/20 ,  F01N3/22 ,  F01N3/30 ,  F01N11/00 ,  F01N13/0097 ,  F01N2260/04 ,  F01N2570/14 ,  F02B29/0406 ,  F02B37/00 ,  F02B37/168 ,  F02M26/05 ,  F02M26/10 ,  F02M26/28 ,  Y02A50/2344 ,  Y02T10/144

摘要： To provide an exhaust gas purifying system and a control method therefor, capable of burning and removing PM collected at the downstream side of a DPF by utilizing HC and CO generated when performing the operation for recovering the NOx direct reduction type catalyst from a catalyst deterioration due to poisoning with sulfur. The exhaust gas purifying system (10) having a NOx direct reduction type catalyst (3) for purging NOx in an exhaust gas and a DPF (4) with a catalyst for purging PM in the exhaust gas are sequentially arranged in an exhaust gas passage (2) in that order in the direction of from an upstream side to a downstream side, which further comprises an air supply system (5) for supplying air (Aa) between the NOx direct reduction type catalyst (3) and the DPF (4) with a catalyst during a operation for recovering the NOx direct reduction type catalyst (3) from a catalyst deterioration due to poisoning with sulfur by bringing the oxygen concentration in the exhaust gas to be substantially zero and raising the exhaust gas temperature.

摘要翻译： 为了提供一种废气净化系统及其控制方法，能够通过利用由催化剂劣化进行NOx还原型催化剂的回收操作而产生的HC和CO燃烧除去在DPF的下游侧收集的PM 用硫中毒。 具有用于排出废气中的NOx的NOx直接还原型催化剂（3）的排气净化系统（10）和排气中的用于除去PM的催化剂的DPF（4）排列在排气通路 2）从上游侧到下游侧的顺序，其还包括用于在NOx直接还原型催化剂（3）和DPF（4）之间供应空气（Aa）的供气系统（5） 在通过使废气中的氧浓度基本上为零并且提高废气温度的情况下，在由于硫的中毒引起的催化剂劣化的操作中，催化剂用于回收NOx直接还原型催化剂（3）。

公开(公告)号：US06725832B2

公开(公告)日：2004-04-27

申请号：US10303533

申请日：2002-11-25

申请人： Jin Yokoyama ,  Yutaka Uematsu

发明人： Jin Yokoyama ,  Yutaka Uematsu

IPC分类号： F02M2507

CPC分类号： F02D41/0052 ,  F02B3/06 ,  F02B23/0672 ,  F02B29/0406 ,  F02D35/0007 ,  F02D41/187 ,  F02D2041/0017 ,  F02D2041/2027 ,  F02D2200/0404 ,  F02M26/05 ,  F02M26/10 ,  F02M26/23 ,  F02M26/53 ,  Y02T10/125 ,  Y02T10/47

摘要： Adequate controllability is ensured when feedback control is provided to both the EGR valve and the intake throttle valve, and switching shock is prevented when control is switched from one to the other. The present apparatus comprises an EGR valve, an intake throttle valve, feedback control means for providing feedback control to the EGR valve and intake throttle valve such that the actual EGR volume approximates the target EGR volume corresponding to the running condition of the engine, and limiting means for limiting the operable opening ranges of the EGR valve and intake throttle valve in accordance with the target EGR volume. During EGR control of one valve, feedback control is provided to the other valve and the target opening is constantly calculated. The actual operations are merely limited, so these operations can start from the optimal opening and the switching shock can be prevented when a switch is made to the control of the other valve.

摘要翻译： 当向EGR阀和进气节流阀提供反馈控制时，确保了足够的可控性，并且当控制从一个切换到另一个时防止了切换冲击。 本发明的装置包括EGR阀，进气节流阀，用于向EGR阀和进气节流阀提供反馈控制的反馈控制装置，使得实际EGR体积接近于对应于发动机的运行状态的目标EGR容积，并限制 用于根据目标EGR容积限制EGR阀和进气节气门的可操作开启范围的装置。 在一个阀的EGR控制期间，向另一个阀提供反馈控制，并且不断地计算目标开度。 实际操作仅限于此，这些操作可以从最佳打开开始，并且当切换到另一个阀的控制时可以防止切换冲击。

公开(公告)号：US4893313A

公开(公告)日：1990-01-09

申请号：US323400

申请日：1989-03-14

申请人： Genichi Hatakoshi ,  Kazuhiko Itaya ,  Shigeya Naritsuka ,  Masayuki Ishikawa ,  Hajime Okuda ,  Hideo Shiozawa ,  Yukio Watanabe ,  Yasuo Ohba ,  Yoshihiro Kokubun ,  Yutaka Uematsu

发明人： Genichi Hatakoshi ,  Kazuhiko Itaya ,  Shigeya Naritsuka ,  Masayuki Ishikawa ,  Hajime Okuda ,  Hideo Shiozawa ,  Yukio Watanabe ,  Yasuo Ohba ,  Yoshihiro Kokubun ,  Yutaka Uematsu

IPC分类号： H01S5/20 ,  H01S5/223 ,  H01S5/32 ,  H01S5/323

CPC分类号： H01S5/32325 ,  H01S5/2004 ,  H01S5/2231 ,  H01S5/3211

摘要： In a semiconductor laser device, for emitting a laser beam having a wavelength .lambda., an n-type In.sub.0.5 (Ga.sub.1-x Al.sub.x)P first cladding layer is formed on an n-type GaAs substrate. An undoped InGaP active layer is formed on the first cladding layer and a p-type In.sub.0.5 (Ga.sub.1-x Al.sub.x).sub.0.5 P cladding layer is formed on the active layer. A p-type InGaP cap layer is formed on the second cladding layer and an n-type GaAs current restricting layer is formed on the second cladding layer. The aluminum composition ratio x of the cladding layer is 0.7. The active layer has a thickness of 0.06 .mu.m and the cladding layers have the same thickness H of 0.85 .mu.m. The active layer and the cladding layers have refractive indices n.sub.a and n.sub.c which satisfies the following inequalities:0.015.DELTA..sup.1/2

公开(公告)号：US08988160B2

公开(公告)日：2015-03-24

申请号：US13004609

申请日：2011-01-11

申请人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

发明人： Yasuhiro Ikeda ,  Yutaka Uematsu ,  Satoshi Muraoka

IPC分类号： H03H2/00 ,  H03H7/38 ,  H04B3/02

CPC分类号： H04B3/02

摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).

摘要翻译： 提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。 通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。