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公开(公告)号：US11955587B2
公开(公告)日：2024-04-09
申请号：US17227391
申请日：2021-04-12
Applicant: Unimicron Technology Corp.
Inventor： Jeng-Ting Li , Chi-Hai Kuo , Cheng-Ta Ko , Pu-Ju Lin
CPC classification number: H01L33/62 , H01L27/156 , H01L33/005 , H01L2933/0066
Abstract: A light emitting diode (LED) package structure includes a glass substrate, conductive through holes, active elements, an insulating layer, LEDs and pads. The glass substrate has an upper surface and a lower surface. The conductive through holes penetrate the glass substrate and connect the upper and the lower surfaces. The active elements are disposed on the upper surface of the glass substrate and electrically connected to the conductive through holes. The insulating layer is disposed on the upper surface and covers the active elements. The LEDs are disposed on the insulating layer and electrically connected to at least one of the active elements. The pads are disposed on the lower surface of the glass substrate and electrically connected to the conductive through holes. A source of at least one active elements is directly electrically connected to at least one of the corresponding pads through the corresponding conductive through hole.
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公开(公告)号：US11937366B2
公开(公告)日：2024-03-19
申请号：US17701964
申请日：2022-03-23
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Tzu Hsuan Wang , Yu Cheng Lin
IPC: H05K1/02
CPC classification number: H05K1/024 , H05K1/0242 , H05K1/0251 , H05K1/0298 , H05K2201/0187 , H05K2201/0195
Abstract: A method of a circuit signal enhancement of a circuit board comprises the following steps: forming a first substrate body with a first signal transmission circuit layer and a second substrate body with a second signal transmission circuit layer; forming a first signal enhancement circuit layer and a second signal enhancement circuit layer on the first substrate body and the second substrate body; forming a third substrate body with a third signal transmission circuit layer and a fourth substrate body with a fourth signal transmission circuit layer on the carrier; separating the third substrate body and the fourth substrate body from the carrier; combining the first signal transmission circuit layer and the third signal transmission circuit layer through the first signal enhancement circuit layer; and combining the second signal transmission circuit layer and the fourth signal transmission circuit layer through the second signal enhancement circuit layer.
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公开(公告)号：US11924961B2
公开(公告)日：2024-03-05
申请号：US17661284
申请日：2022-04-28
Applicant: Unimicron Technology Corp.
Inventor： Ai Jing Lin , Chung-Yu Lan , Jia Hao Liang
CPC classification number: H05K1/0204 , H05K1/115 , H05K3/0061 , H05K2201/09509 , H05K2201/10416
Abstract: A circuit board includes a conductive metal layer, at least one insulating layer, at least one thermally conductive insulating layer and a heat dissipation element. The conductive metal layer is mainly used to transmit electronic signals. The insulating layer is connected to the conductive metal layer. The thermally conductive insulating layer is sandwiched between the conductive metal layer and the insulating layer, and thermally contacts the conductive metal layer, and is used for thermally conducting the heat of the conductive metal layer. The heat dissipation element is in thermal contact with the thermally conductive insulating layer, and is used to conduct the heat of the thermally conductive insulating layer to the outside through a heat dissipation channel.
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公开(公告)号：US20230420818A1
公开(公告)日：2023-12-28
申请号：US18121476
申请日：2023-03-14
Applicant: UNIMICRON TECHNOLOGY CORP , TUNGHAI UNIVERSITY
Inventor： Chi-Feng CHEN , Po-Sheng YEN , Ruey-Beei WU , Ra-Min TAIN , Chin-Sheng WANG , Jun-Ho CHEN
IPC: H01P1/203
CPC classification number: H01P1/20309
Abstract: A multi-layered resonator circuit structure and a multi-layered filter circuit structure. The multi-layered resonator circuit structure includes a multi-layered substrate, a plurality of resonators and a plurality of conductive components. The multi-layered substrate has a top surface, a bottom surface, and a ground layer. The top surface and the bottom surface face away from each other. The ground layer is located between the top surface and the bottom surface. A part of the plurality of resonators is/are disposed on the top surface. Another part of the plurality of resonators is/are disposed on the bottom surface. The plurality of conductive components is located in the multi-layered substrate. The plurality of resonators is electrically connected to the ground layer, respectively, via the plurality of conductive components.
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公开(公告)号：US11837591B2
公开(公告)日：2023-12-05
申请号：US17714121
申请日：2022-04-05
Applicant: Unimicron Technology Corp.
Inventor： Ming-Ru Chen , Tzyy-Jang Tseng , Cheng-Chung Lo
CPC classification number: H01L25/167 , H01L33/62 , H01L33/56 , H01L2933/0066
Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
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Patent Agency Ranking
公开(公告)号：US20230335466A1
公开(公告)日：2023-10-19
申请号：US18337438
申请日：2023-06-20
Applicant: Unimicron Technology Corp.
Inventor： Chin-Sheng Wang , Ra-Min Tain , Chih-Kai Chan , Jun-Ho Chen
CPC classification number: H01L23/481 , H01L23/66 , H05K1/189 , H05K3/4691 , H05K3/4697 , H05K1/0216 , H01L2223/6677 , H05K2201/10098 , H05K2201/0154 , H05K2201/09809
Abstract: An electronic packaging structure including a first circuit structure, a second circuit structure and at least one electronic device is provided. The bottom side of the first circuit structure has at least one cavity. The first circuit structure is disposed on the second circuit structure. The first circuit structure and the second circuit structure are electrically connected to each other. The electronic device is disposed on the second circuit structure. The electronic device is disposed corresponding to the cavity of the first circuit structure.
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公开(公告)号：US20230262880A1
公开(公告)日：2023-08-17
申请号：US18162713
申请日：2023-02-01
Applicant: Unimicron Technology Corp.
Inventor： Chih-Chiang Lu , Jun-Rui Huang , Ming-Hao Wu , Tung-Chang Lin
CPC classification number: H05K1/025 , H05K1/112 , H05K1/0216 , H05K2201/095
Abstract: Provided is a circuit board structure including a substrate, a loop-wrapping ground layer, an insulating structure, a first build-up layer, a top wiring layer, a bottom wiring layer, a first conductive via, and a plurality of second conductive vias. The aforementioned structure defines a signal transmitting structure. An equivalent circuit of the signal transmitting structure at least includes a first equivalent circuit, a second equivalent circuit, a third equivalent circuit and a fourth equivalent circuit, which correspond to different uniform transmitting sections respectively. The first equivalent circuit, the second equivalent circuit, the third equivalent circuit and the fourth equivalent circuit are connected in series with each other according to an ABCD transmission matrix series connection principle.
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公开(公告)号：US20230225050A1
公开(公告)日：2023-07-13
申请号：US17899583
申请日：2022-08-30
Applicant: Unimicron Technology Corp.
Inventor： Kuang-Ching Fan , Chih-Peng Hsieh , Cheng-Hsiung Wang
CPC classification number: H05K1/112 , H05K3/4644
Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to ¼ of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.
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公开(公告)号：US11678441B2
公开(公告)日：2023-06-13
申请号：US16950910
申请日：2020-11-18
Applicant: Unimicron Technology Corp.
Inventor： Wei-Ti Lin , Chun-Hsien Chien , Chien-Chou Chen , Fu-Yang Chen , Ra-Min Tain
CPC classification number: H05K3/4644 , H05K1/111 , H05K1/115 , H05K1/181 , H05K3/007 , H05K3/0097 , H05K3/28 , H05K3/303 , H05K3/4007 , H05K3/421 , H05K3/429 , H05K2201/09136 , H05K2201/09509 , H05K2201/09827 , H05K2201/10234 , H05K2201/10522
Abstract: A circuit carrier board structure includes a first substrate, a second substrate, an adhesive layer, and a plurality of contact pads. The first substrate includes a first surface and a second surface, and also includes a plurality of first build-up layers sequentially stacked. The first build-up layers include a first dielectric layer and a first circuit layer. The second substrate includes a third surface and a fourth surface, and also includes a plurality of second build-up layers sequentially stacked. The second build-up layers include a second dielectric layer and a second circuit layer. The second surface is combined to the third surface. The connection pads are on the first surface and electrically connected to the first circuit layer. The first substrate is electrically connected to the second substrate. A manufacturing method of the circuit carrier board structure is also provided.
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公开(公告)号：US11670520B2
公开(公告)日：2023-06-06
申请号：US17523093
申请日：2021-11-10
Applicant: UNIMICRON TECHNOLOGY CORP.
Inventor： Jia Shiang Chen , Chung-Yu Lan , Yu-Shen Chen
IPC: H01L21/00 , H01L21/48 , H01L23/538 , H01L23/498 , H05K1/18 , H01L25/065
CPC classification number: H01L21/486 , H01L23/49805 , H01L23/5384 , H01L25/0657 , H05K1/182 , H05K1/186 , H01L2225/06517 , H01L2225/06572
Abstract: A packaging method includes steps of: forming first and second wiring layers electrically connected to each other on two opposite surfaces of a substrate; then configuring mother substrate interconnecting bumps on the first wiring layer and along perimeter of a daughter substrate unit, and then cutting along the perimeter of the daughter substrate unit to expose lateral faces of the mother substrate interconnecting bumps and configuring solder materials thereon; then configuring first and second chips on the first and the second wiring layers to form electrical interconnection between the two chips. A package structure enables interconnecting two chips through one single daughter substrate unit with its wiring layers directly connecting with lateral face contacts of the mother carrier substrate through the mother substrate interconnecting bumps. Hence, area of the daughter substrate unit is reduced; lengths of the interconnection paths are shortened, and qualities of communication and space utilization are enhanced.
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