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公开(公告)号：US20090272172A1
公开(公告)日：2009-11-05
申请号：US12431213
申请日：2009-04-28
Applicant: Yeau-Ren Jeng , Chung-Ming Tan
Inventor： Yeau-Ren Jeng , Chung-Ming Tan
IPC: B21D31/00
CPC classification number: B81C1/00031 , B81B2201/07 , B82Y10/00 , G11B9/149 , Y10T29/49147 , Y10T29/49151 , Y10T29/49155
Abstract: The present invention discloses a method for generating nano patterns upon material surfaces. The method for generating nano patterns upon material surfaces comprises the following steps: providing a thin film capable of controlling lattice directions, applying a nanoindentation action to the thin film to generate an indentation at a specific position on the thin film. At least one hillock is then generated in a specific direction to generate a pattern and to be applied to a data storage system.
Abstract translation: 本发明公开了一种在材料表面上产生纳米图案的方法。 在材料表面上产生纳米图案的方法包括以下步骤：提供能够控制晶格方向的薄膜，对薄膜施加纳米压痕作用以在薄膜上的特定位置产生凹陷。 然后在特定方向上产生至少一个小丘以产生模式并应用于数据存储系统。
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公开(公告)号：US20080029169A1
公开(公告)日：2008-02-07
申请号：US11463241
申请日：2006-08-08
Applicant: Sebastian J. Maerkl , Todd A. Thorsen , Xiaoyan Bao , Stephen R. Quake , Vincent Studer
Inventor： Sebastian J. Maerkl , Todd A. Thorsen , Xiaoyan Bao , Stephen R. Quake , Vincent Studer
IPC: F16K11/20
CPC classification number: C12Q1/28 , B01L3/5025 , B01L3/50273 , B01L3/502738 , B01L2300/0861 , B01L2300/0887 , B01L2400/0481 , B01L2400/0655 , B81B2201/0214 , B81B2201/054 , B81B2201/07 , B81C1/00119 , F15C5/00 , F16K11/20 , F16K99/0001 , F16K99/0015 , F16K99/0059 , F16K2099/0074 , F16K2099/0076 , F16K2099/0078 , F16K2099/008 , F16K2099/0084 , F16K2099/0094 , Y10T137/0318 , Y10T137/0329 , Y10T137/2224 , Y10T137/85938 , Y10T137/87249
Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.
Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个单独可寻址腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组件是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。
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公开(公告)号：US12101932B2
公开(公告)日：2024-09-24
申请号：US17450729
申请日：2021-10-13
Applicant: Micron Technology, Inc.
Inventor： Erwin E. Yu , Surendranath C. Eruvuru , Yoshiaki Fukuzumi , Tomoko Ogura Iwasaki
CPC classification number: H10B41/41 , B81B7/02 , G11C7/1012 , G11C16/24 , H10B41/20 , H10B43/20 , H10B43/40 , B81B2201/07
Abstract: A microelectronic device comprises a stack structure, first digit lines, second digit lines, and multiplexer devices. The stack structure comprises an access line region comprising a lower group of conductive structures, and a select gate region overlying the access line region and comprising an upper group of conductive structures. The first digit lines are coupled to strings of memory cells, and the second digit lines are coupled to additional strings of memory cells. The second digit lines are horizontally offset from the first digit lines in a first direction and are substantially horizontally aligned with the first digit lines in a second direction. The multiplexer devices are coupled to page buffer devices, the first digit lines, and the second digit lines. The multiplexer devices comprise transistors in electrical communication with the upper group of conductive structures. Additional microelectronic devices, memory devices, and electronic systems are also described.
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公开(公告)号：US11997430B2
公开(公告)日：2024-05-28
申请号：US17146363
申请日：2021-01-11
Applicant: Texas Instruments Incorporated
Inventor： Noah Alan Robb , Harsh Dinesh Jhaveri , Priyankar Mathuria
CPC classification number: H04N9/312 , B81B7/02 , G02B26/0816 , G02B26/0833 , G02B26/105 , G11C5/063 , G11C11/413 , H04N9/3152 , B81B2201/042 , B81B2201/07
Abstract: In a described example, a device includes: a semiconductor substrate; a memory array on the semiconductor substrate, the memory array comprising rows and columns of memory cells in a Manhattan pattern, the memory cells having a pitch in a direction along the columns; and an array of micromirrors in a diamond pattern over the memory cells, the micromirrors coupled to corresponding memory cells, the micromirrors having a diagonal pitch length in the direction along the columns that is between 1.8 times the pitch and 2.2 times the pitch.
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公开(公告)号：US20180012972A1
公开(公告)日：2018-01-11
申请号：US15695440
申请日：2017-09-05
Applicant: Purdue Research Foundation
Inventor： Muhammad Ashraful Alam , Muhammad Masuduzzaman , Ankit Jain
IPC: H01L29/51 , H01G7/06 , H01G4/38 , H01G5/40 , H01L27/08 , B81B7/02 , H01L29/78 , H01G5/16 , H01L49/02
CPC classification number: H01L29/515 , B81B7/02 , B81B2201/014 , B81B2201/016 , B81B2201/07 , H01G4/38 , H01G5/16 , H01G5/40 , H01G7/06 , H01L27/0805 , H01L27/11502 , H01L27/11585 , H01L29/516 , H01L29/7842
Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
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Patent Agency Ranking
公开(公告)号：US20100315938A1
公开(公告)日：2010-12-16
申请号：US12192006
申请日：2008-08-14
Applicant: Peter David Ascanio , Tom P. Frangesh
Inventor： Peter David Ascanio , Tom P. Frangesh
CPC classification number: G11B9/1436 , B81B7/0051 , B81B2201/038 , B81B2201/07 , B81B2201/11 , H01L2924/0002 , H02K5/04 , H02K99/20 , Y10T29/49 , H01L2924/00
Abstract: A package to receive a memory device including an electromagnetic motor comprises a body having a top surface and a bottom surface. Conductive leads extend through the body so that the conductive leads are at least partially exposed within the package. A base is connectable with the bottom surface of the body, and a lid is connectable with the top surface of the body. The base and the lid have substantially matched thermal expansion characteristics and provide magnetic flux return paths for the electromagnetic motor.
Abstract translation: 用于接收包括电磁电动机的存储装置的包装件包括具有顶表面和底表面的主体。 导电引线延伸穿过主体，使得导电引线至少部分地暴露在封装内。 基座可与主体的底面连接，盖可与主体的上表面连接。 基座和盖具有基本上匹配的热膨胀特性，并为电磁马达提供磁通返回路径。
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公开(公告)号：US07522029B1
公开(公告)日：2009-04-21
申请号：US12179302
申请日：2008-07-24
Applicant: Mark Alfred Lantz
Inventor： Mark Alfred Lantz
CPC classification number: H01H61/01 , B81B3/0072 , B81B2201/07 , B81B2203/0118 , B81C2201/0167 , H01H2061/006
Abstract: An actuator is provided. The actuator comprises a base portion, a cantilever beam connected to the base portion, and an actuator cell adjacent to the cantilever beam. The actuator cell comprises a first metal electrode positioned on the cantilevered beam, a second metal electrode positioned near the first metal electrode, and phase change material between the first and second metal electrodes, wherein the phase change material connects the first metal electrode to the second metal electrode, wherein applying a burst of energy to the phase change material causes the phase change material to change between an amorphous state and a crystalline state, causing the cantilevered beam to move between a first position and a target position, wherein the cantilevered beam remains at the target position upon removal of the energy.
Abstract translation: 提供一个致动器。 致动器包括基部，连接到基部的悬臂梁和与悬臂梁相邻的致动器单元。 所述致动器单元包括位于所述悬臂梁上的第一金属电极，位于所述第一金属电极附近的第二金属电极以及所述第一和第二金属电极之间的相变材料，其中所述相变材料将所述第一金属电极连接到所述第二金属电极 金属电极，其中向所述相变材料施加能量爆发导致所述相变材料在非晶状态和结晶态之间变化，导致所述悬臂梁在第一位置和目标位置之间移动，其中所述悬臂梁保持 在去除能量时在目标位置。
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公开(公告)号：US20090001486A1
公开(公告)日：2009-01-01
申请号：US11824465
申请日：2007-06-29
Applicant: John Heck , Tsung-Kuan Allen Chou
Inventor： John Heck , Tsung-Kuan Allen Chou
CPC classification number: B81C1/00246 , B81B2201/07 , B81B2201/11 , B81B2201/12 , B81B2203/0118 , B81C2203/0735 , B82Y10/00 , G11B9/1436
Abstract: In one embodiment, the present invention includes a method for forming a sacrificial oxide layer on a base layer of a microelectromechanical systems (MEMS) probe, patterning the sacrificial oxide layer to provide a first trench pattern having a substantially rectangular form and a second trench pattern having a substantially rectangular portion and a lateral portion extending from the substantially rectangular portion, and depositing a conductive layer on the patterned sacrificial oxide layer to fill the first and second trench patterns to form a support structure for the MEMS probe and a cantilever portion of the MEMS probe. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括在微机电系统（MEMS）探针的基底层上形成牺牲氧化物层的方法，图案化牺牲氧化物层以提供具有基本矩形形状的第一沟槽图案和第二沟槽图案 具有基本上矩形的部分和从所述大致矩形部分延伸的横向部分，以及在所述图案化的牺牲氧化物层上沉积导电层以填充所述第一和第二沟槽图案以形成用于所述MEMS探针的支撑结构， MEMS探针。 描述和要求保护其他实施例。
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公开(公告)号：US07143785B2
公开(公告)日：2006-12-05
申请号：US10670997
申请日：2003-09-24
Applicant: Sebastian J. Maerkl , Todd A. Thorsen , Xiaoyan Bao , Stephen R. Quake , Vincent Studer
Inventor： Sebastian J. Maerkl , Todd A. Thorsen , Xiaoyan Bao , Stephen R. Quake , Vincent Studer
CPC classification number: C12Q1/28 , B01L3/5025 , B01L3/50273 , B01L3/502738 , B01L2300/0861 , B01L2300/0887 , B01L2400/0481 , B01L2400/0655 , B81B2201/0214 , B81B2201/054 , B81B2201/07 , B81C1/00119 , F15C5/00 , F16K11/20 , F16K99/0001 , F16K99/0015 , F16K99/0059 , F16K2099/0074 , F16K2099/0076 , F16K2099/0078 , F16K2099/008 , F16K2099/0084 , F16K2099/0094 , Y10T137/0318 , Y10T137/0329 , Y10T137/2224 , Y10T137/85938 , Y10T137/87249
Abstract: High-density microfluidic chips contain plumbing networks with thousands of micromechanical valves and hundreds of individually addressable chambers. These fluidic devices are analogous to electronic integrated circuits fabricated using large scale integration (LSI). A component of these networks is the fluidic multiplexor, which is a combinatorial array of binary valve patterns that exponentially increases the processing power of a network by allowing complex fluid manipulations with a minimal number of inputs. These integrated microfluidic networks can be used to construct a variety of highly complex microfluidic devices, for example the microfluidic analog of a comparator array, and a microfluidic memory storage device resembling electronic random access memories.
Abstract translation: 高密度微流控芯片包含具有数千个微机械阀门和数百个单独可寻址腔室的管道网络。 这些流体装置类似于使用大规模集成（LSI）制造的电子集成电路。 这些网络的一个组件是流体多路复用器，它是二进制阀模式的组合阵列，通过允许使用最少数量的输入的复杂流体操纵来指数地增加网络的处理能力。 这些集成的微流体网络可用于构建各种高度复杂的微流体装置，例如比较器阵列的微流体模拟装置和类似于电子随机存取存储器的微流体存储器存储装置。
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公开(公告)号：US20160207761A1
公开(公告)日：2016-07-21
申请号：US14701502
申请日：2015-04-30
Applicant: Purdue Research Foundation
Inventor： Muhammad Ashraful Alam , Muhammad Masuduzzaman , Ankit Jain
CPC classification number: H01L29/515 , B81B7/02 , B81B2201/014 , B81B2201/016 , B81B2201/07 , H01G4/38 , H01G5/16 , H01G5/40 , H01G7/06 , H01L27/0805 , H01L27/11502 , H01L27/11585 , H01L29/516 , H01L29/7842
Abstract: An electrical circuit comprising at least two negative capacitance insulators connected in series, one of the two negative capacitance insulators is biased to generate a negative capacitance. One of the negative capacitance insulators may include an air-gap which is part of a nanoelectromechnical system (NEMS) device and the second negative capacitance insulator includes a ferroelectric material. Both of the negative capacitance insulators may be located between the channel and gate of a field effect transistor. The NEMS device may include a movable electrode, a dielectric and a fixed electrode and arranged so that the movable electrode is attached to at least two points and spaced apart from the dielectric and fixed electrode, and the ferroelectric capacitor is electrically connected to either of the electrodes.
Abstract translation: 包括串联连接的至少两个负电容绝缘体的电路，两个负电容绝缘体之一被偏置以产生负电容。 负电容绝缘体中的一个可以包括作为纳米电子技术系统（NEMS）器件的一部分的气隙，并且第二负电容绝缘体包括铁电材料。 负电容绝缘体都可以位于场效应晶体管的沟道和栅极之间。 NEMS装置可以包括可动电极，电介质和固定电极，并且布置成使得可动电极附接到至少两个点并且与电介质和固定电极间隔开，并且铁电电容器电连接到 电极。
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