公开(公告)号：US11699765B2

公开(公告)日：2023-07-11

申请号：US17461034

申请日：2021-08-30

申请人： Samsung Electronics Co., Ltd.

发明人： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC分类号： H01L29/86 ,  H10K10/50 ,  H10K19/00 ,  H10B69/00

CPC分类号： H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

摘要： A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20230155018A1

公开(公告)日：2023-05-18

申请号：US18092727

申请日：2023-01-03

申请人： Monolithic 3D Inc.

发明人： Zvi Or-Bach

IPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00

CPC分类号： H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B69/00 ,  H10B63/30 ,  G11C11/412

摘要： A semiconductor device, the device comprising: a first silicon layer comprising first single crystal silicon; an isolation layer disposed over said first silicon layer; a first metal layer disposed over said isolation layer; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said isolation layer comprises an oxide to oxide bond surface, wherein said plurality of transistors comprise a second single crystal silicon region; and a plurality of capacitors, wherein said plurality of capacitors comprise functioning as a decoupling capacitor to mitigate power supply noise.

公开(公告)号：US12125534B2

公开(公告)日：2024-10-22

申请号：US17935122

申请日：2022-09-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Younggul Song ,  Junyeong Seok ,  Eun Chu Oh ,  Byungchul Jang

IPC分类号： G11C8/00 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B69/00

CPC分类号： G11C16/0483 ,  G11C5/063 ,  G11C16/08 ,  H10B69/00

摘要： A storage device includes a non-volatile memory device. The non-volatile memory device includes a first substrate including a first peripheral circuit region including a row decoder selecting one word line from among a plurality of word lines of a three-dimensional (3D) memory cell array and a second substrate including a second peripheral circuit region, including a page buffer unit selecting at least one bit line from among a plurality of bit lines of the 3D memory cell array, and a cell region including the 3D memory cell array formed in the second peripheral circuit region. The 3D memory cell array is disposed between the first peripheral circuit region and the second peripheral circuit region by vertically stacking and bonding the second substrate on and to the first substrate.

公开(公告)号：US20240194529A1

公开(公告)日：2024-06-13

申请号：US18507019

申请日：2023-11-10

申请人： Micron Technology, Inc.

发明人： Shyam Surthi ,  David H. Wells

IPC分类号： H01L21/768 ,  H01L21/033 ,  H01L21/32 ,  H10B69/00

CPC分类号： H01L21/76897 ,  H01L21/0334 ,  H01L21/32 ,  H01L21/76805 ,  H10B69/00

摘要： Semiconductor devices including self-aligned vertical connectors are disclosed herein. The self-aligned vertical connectors may have upper and lower portions that are concentric or have fixed relative positions across the connectors. The concentric or fixed relative positions may be aligned with a corresponding circuit or a bit line based on forming a conformal depression by depositing a controlled amount of conformal layer that fills wells adjacent to the bit line at a target location of the vertical connector. The vertical connector can be formed using the conformal depression, which may be self-aligned relative to the bit line as a result of filling the wells with the controlled amount of the conformal layer.

公开(公告)号：US11984514B2

公开(公告)日：2024-05-14

申请号：US18324638

申请日：2023-05-26

申请人： Samsung Electronics Co., Ltd.

发明人： Jinseong Heo ,  Taehwan Moon ,  Hagyoul Bae ,  Seunggeol Nam ,  Sangwook Kim ,  Kwanghee Lee

IPC分类号： H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC分类号： H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

摘要： A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20240138159A1

公开(公告)日：2024-04-25

申请号：US18487248

申请日：2023-10-15

申请人： ROHM CO., LTD.

发明人： Takeharu IMAI

IPC分类号： H10B99/00 ,  H10B69/00

CPC分类号： H10B99/14 ,  H10B69/00

摘要： A semiconductor integrated circuit device includes: a terminal; an internal resistor that is any one of a pull-up resistor configured so that a first end of the pull-up resistor is connected to the terminal and a first constant voltage is applied to a second end of the pull-up resistor, or a pull-down resistor configured so that a first end of the pull-down resistor is connected to the terminal and a ground voltage is applied to a second end of the pull-down resistor; and an AD converter configured so that a voltage of the terminal is converted into digital data having a number of bits of 2 or more.

公开(公告)号：US20240096690A1

公开(公告)日：2024-03-21

申请号：US18456623

申请日：2023-08-28

申请人： Kioxia Corporation

发明人： Shingo HONDA

IPC分类号： H01L21/768 ,  H01L23/522 ,  H10B69/00

CPC分类号： H01L21/76804 ,  H01L23/5226 ,  H10B69/00

摘要： A semiconductor device includes a first layer including a first recess portion on an upper surface; and a second recess portion that extends from a bottom surface of the first recess portion in the first layer, and the second recess portion has a tapered shape in which a width in a first direction along a surface direction of the first layer reduces from the bottom surface of the first recess portion in a depth direction of the first layer.

公开(公告)号：US20240040767A1

公开(公告)日：2024-02-01

申请号：US18377794

申请日：2023-10-07

申请人： Zeno Semiconductor, Inc.

发明人： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC分类号： H10B12/00 ,  H01L21/265 ,  G11C16/04 ,  H01L27/088 ,  H01L29/66 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L29/78 ,  G11C5/06 ,  H01L23/528 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/10

CPC分类号： H10B12/20 ,  H01L21/26586 ,  G11C16/0416 ,  H01L27/0886 ,  H01L29/66659 ,  H10B12/50 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00 ,  H01L29/7841 ,  G11C16/0483 ,  G11C5/063 ,  H01L23/528 ,  G11C11/4096 ,  G11C11/4099 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/785 ,  G11C2211/4016

摘要： NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

公开(公告)号：US11869601B2

公开(公告)日：2024-01-09

申请号：US18053271

申请日：2022-11-07

申请人： Kioxia Corporation

发明人： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

IPC分类号： G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H10B69/00

CPC分类号： G11C16/26 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H10B69/00

摘要： A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US11839091B2

公开(公告)日：2023-12-05

申请号：US17011156

申请日：2020-09-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Junhyoung Kim ,  Kwang-Soo Kim ,  Bonghyun Choi ,  Siwan Kim

IPC分类号： H10B43/20 ,  H10B69/00

CPC分类号： H10B69/00 ,  H10B43/20

摘要： A three-dimensional semiconductor memory device including a substrate including a cell array region and a first connection region arranged in a first direction; and a first block structure on the substrate, the first block structure including a lower stack including a plurality of lower electrodes vertically stacked on the substrate; and intermediate stacks exposing the lower stack, the intermediate stacks including a plurality of intermediate electrodes vertically stacked on the lower stack, wherein, on the cell array region, the first block structure has a first width in a second direction crossing the first direction, and wherein, on the first connection region, the first block structure has a second width, which is larger than the first width, in the second direction.