公开(公告)号：US09842832B2

公开(公告)日：2017-12-12

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H05K1/18

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20170301625A1

公开(公告)日：2017-10-19

申请号：US15636117

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Christopher J. Nelson ,  Omkar G. Karhade ,  Feras Eid ,  Nitin A. Deshpande ,  Shawna M. Liff

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/563 ,  H01L21/568 ,  H01L23/145 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/24 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/24145 ,  H01L2224/24245 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/2912 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92242 ,  H01L2224/92244 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/0665

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

公开(公告)号：US20170287664A1

公开(公告)日：2017-10-05

申请号：US15089213

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Feras Eid ,  John J. Beatty

IPC: H01H37/46 ,  H01H37/04 ,  H01H37/64 ,  H01H37/72

CPC classification number: H01H37/46 ,  H01H37/00 ,  H01H37/04 ,  H01H37/48 ,  H01H37/52 ,  H01H37/64 ,  H01H37/72 ,  H01H2001/0078 ,  H01H2001/0084 ,  H01H2037/008

Abstract: Thermal switch technology is disclosed. In one example, a thermally activated switch can include an electronic substrate base, and first and second electrical contacts coupled to the electronic substrate base. The first and second electrical contacts can be movable relative to one another due to thermal expansion or contraction of a material to facilitate contact or separation of the first and second electrical contacts.

公开(公告)号：US09711428B2

公开(公告)日：2017-07-18

申请号：US14914998

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Henning Braunisch ,  Feras Eid ,  Adel A. Elsherbini ,  Johanna M. Swan ,  Don W. Nelson

IPC: H01L23/367 ,  H01L21/52 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L23/3675 ,  H01L21/52 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5389 ,  H01L2924/0002 ,  H05K1/021 ,  H05K1/185 ,  H05K2201/066 ,  H05K2201/10416 ,  H05K2201/10545 ,  H01L2924/00

Abstract: An apparatus including a die, a first side of the die including a first type of system level contact points and a second side including a second type of contact points; and a package substrate coupled to the die and the second side of the die. An apparatus including a die, a first side of the die including a plurality of system level logic contact points and a second side including a second plurality of system level power contact points. A method including coupling one of a first type of system level contact points on a first side of a die and a second type of system level contact points on a second side of the die to a package substrate.

公开(公告)号：US20160300824A1

公开(公告)日：2016-10-13

申请号：US15183179

申请日：2016-06-15

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  John S. Guzek ,  Johanna M. Swan ,  Christopher J. Nelson ,  Nitin A. Deshpande ,  William J. Lambert ,  Charles A. Gealer ,  Feras Eid ,  Islam A. Salama ,  Kemal Aygun ,  Sasha N. Oster ,  Tyler N. Osborn

IPC: H01L25/16 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/16 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/50 ,  H01L24/86 ,  H01L25/00 ,  H01L25/0655 ,  H01L2224/0405 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/29078 ,  H01L2224/86203 ,  H01L2224/86815 ,  H05K1/185 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

公开(公告)号：US20160171869A1

公开(公告)日：2016-06-16

申请号：US14567625

申请日：2014-12-11

Applicant: INTEL CORPORATION

Inventor： Jessica Gullbrand ,  Melissa A. Cowan ,  Chytra Pawashe ,  Feras Eid

IPC: G08B21/18 ,  F15D1/00

CPC classification number: G08B21/182 ,  F15D1/0095 ,  G01N1/2273 ,  G01N1/24 ,  G01N2001/242 ,  G08B21/12 ,  G08B25/08 ,  H01L23/4735 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to deliver a controlled airflow or other fluidic flow to a sensor measurement area. Such a sensing system can be used to detect accurate concentration of target features present in the ambient surroundings, such as gases, particles, solutions, mixtures, and any other environmental features that can be sensed from a controlled airflow. An example application is air quality monitoring by using one or more synthetic jet devices to deliver a known or otherwise controlled airflow to a sensing area, thereby allowing for detection of harmful or otherwise unacceptable concentrations of particulate matter, gases, or air pollutants. In some embodiments, a synthetic jet device is operatively coupled with a sensor via a flow channel in a common housing, so as to provide a controlled flow sensing system.

Abstract translation: 公开了使用合成射流技术作为感测应用的空气输送装置的技术。 特别地，合成喷射装置用于将可控气流或其它流体流传送到传感器测量区域。 这种感测系统可用于检测周围环境中存在的目标特征的精确浓度，例如气体，颗粒，溶液，混合物以及可从可控气流中感测到的任何其它环境特征。 示例性应用是通过使用一个或多个合成喷射装置将已知或以其它方式控制的气流传送到感测区域进行空气质量监测，从而允许检测有害或其他不可接受的颗粒物质，气体或空气污染物的浓度。 在一些实施例中，合成喷射装置通过公共壳体中的流动通道与传感器可操作地耦合，以便提供受控的流量感测系统。

公开(公告)号：US20150189797A1

公开(公告)日：2015-07-02

申请号：US14126271

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Sasha Oster ,  Sarah Haney ,  Weng Hong Teh ,  Feras Eid

IPC: H05K9/00 ,  B81B7/02 ,  B32B38/10 ,  H05K1/11 ,  B32B37/24 ,  B81B7/00 ,  G06F1/18

CPC classification number: H05K9/0052 ,  B32B37/24 ,  B32B38/10 ,  B32B2037/243 ,  B32B2457/00 ,  B81B7/0029 ,  B81B7/0032 ,  B81B7/02 ,  B81C1/0023 ,  G06F1/182 ,  H01L21/568 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H05K1/115 ,  Y10T156/10 ,  H01L2924/00

Abstract: Magnetic field shielding material with high relative permeability incorporated into a build-up package, for example to restrict a field of a magnet integrated with the build-up to a target device configured to operate in the field. In embodiments, a first device is physically coupled to the build-up. In embodiments, a magnetic field shielding material is disposed in contact with the build-up and in proximity to the first device to restrict a magnetic field either to a region occupied by the first device or to a region exclusive of the first device. A field shielding material may be disposed within build-up near a permanent magnet also within the build-up to reduce exposure of another device, such as an IC, to the magnetic field without reducing MEMS device exposure.

Abstract translation: 具有高的相对磁导率的磁场屏蔽材料被并入到积聚封装中，例如将与积聚物集成的磁体的场限制到被配置为在现场操作的目标装置。 在实施例中，第一设备物理地耦合到建立。 在实施例中，磁场屏蔽材料设置成与积层接触并且靠近第一装置，以将磁场限制到由第一装置占据的区域或不包括第一装置的区域。 场屏蔽材料也可以在堆积物内的永磁体附近的堆积内设置，以减少诸如IC之类的其它器件（例如IC）的暴露，而不会降低MEMS器件的暴露。

公开(公告)号：US20250112218A1

公开(公告)日：2025-04-03

申请号：US18478831

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon M. Rawlings ,  Adel Elsherbini ,  Thomas L. Sounart ,  Feras Eid ,  Tushar Kanti Talukdar ,  Kimin Jun ,  Johanna Swan ,  Richard F. Vreeland

IPC: H01L25/00 ,  H01L21/683 ,  H01L25/075

Abstract: In one embodiment, a selective layer transfer process includes forming a layer of integrated circuit (IC) components on a first substrate, forming first bonding structures on a second substrate, and partially bonding the first substrate to the second substrate, which includes bonding a first subset of IC components on the first substrate to respective bonding structures on the second substrate. The process also includes forming second bonding structures on a third substrate, where the second bonding structures are arranged in a layout that is offset from the layout of the second substrate. The process further includes partially bonding the first substrate to the third substrate, which includes bonding a second subset of IC components on the first substrate to respective bonding structures on the third substrate.

公开(公告)号：US20250112185A1

公开(公告)日：2025-04-03

申请号：US18374515

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Michael Baker ,  Seyed Hadi Zandavi ,  Yi Shi ,  Feras Eid

IPC: H01L23/00

Abstract: Hybrid bonded die stacks, related apparatuses, systems, and methods of fabrication are disclosed. One or both of an integrated circuit (IC) die hybrid bonding region and a base substrate hybrid bonding region are surrounded by superhydrophobic structures that have a contact angle not less than 150 degrees. The hybrid bonding regions are brought together with a liquid droplet therebetween, and capillary forces cause the IC die to self-align. The liquid droplet is pinned to the hybrid bonding regions by the superhydrophobic structures. A hybrid bond is formed by evaporating the droplet and a subsequent anneal.

公开(公告)号：US20250112127A1

公开(公告)日：2025-04-03

申请号：US18374573

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Feras Eid ,  Adel Elsherbini ,  Veronica Strong ,  Thomas Sounart

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/498 ,  H01L23/528

Abstract: A surface finish on an integrated circuit (IC) die structure or a substrate structure to which an IC die structure is to be bonded has a chemical composition distinct from that of underlying metallization. The surface finish may comprise a Cu—Ni alloy. Optionally, the Cu—Ni alloy may further comprise Mn. Alternatively, the surface finish may comprise a noble metal, such as Pd, Pt, or Ru or may comprise self-assembled monolayer (SAM) molecules comprising Si and C. During the bonding process a biphilic surface on the IC die structure or substrate structure may facilitate liquid droplet-based fine alignment of the IC die structure to a host structure. Prior to bonding, the surface finish may be applied upon a top surface of metallization features and may inhibit oxidation of the top surface exposed to the liquid droplet.