公开(公告)号：US09479152B2

公开(公告)日：2016-10-25

申请号：US13894783

申请日：2013-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshikazu Kondo ,  Jun Koyama

IPC: H03K17/00 ,  G11C5/14 ,  H03K19/00

CPC classification number: H03K17/00 ,  G11C5/148 ,  H03K19/0008 ,  Y10T307/858

Abstract: A semiconductor device capable of simply performing power gating and a driving method thereof are provided. Power gating is started passively (automatically in the case of satisfying predetermined conditions). Specifically, the semiconductor device includes a transistor for selecting whether a power source voltage is supplied or not to a functional circuit. The power gating is started by turning off the transistor in the case where a voltage between a source and a drain is less than or equal to a predetermined voltage. Therefore, complicated operation is not needed at the time of starting power gating. Specifically, it is possible to start power gating without a process for predicting the timing at which an arithmetic operation performed in the functional circuit is terminated. As a result, it is possible to start power gating easily.

Abstract translation: 提供能够简单地执行电源门控的半导体器件及其驱动方法。 电力门控被动地开始（在满足预定条件的情况下自动）。 具体地，半导体器件包括用于选择是否向功能电路提供电源电压的晶体管。 在源极和漏极之间的电压小于或等于预定电压的情况下，通过关断晶体管来开始电源门控。 因此，在启动电源门控时不需要复杂的操作。 具体地说，可以在没有用于预测在功能电路中进行的算术运算结束的定时的处理的情况下开始电力门控。 因此，可以轻松启动电源门控。

公开(公告)号：US09479143B2

公开(公告)日：2016-10-25

申请号：US14670536

申请日：2015-03-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun Koyama

IPC: G11C11/24 ,  G11C7/10 ,  G11C5/14 ,  G11C8/00 ,  H03K3/012 ,  G11C8/04 ,  H03K3/037 ,  H01L21/8258 ,  H01L27/088 ,  H01L29/786 ,  H01L27/12 ,  H03K19/00 ,  H01L27/06 ,  H01L29/04 ,  H01L21/8234

Abstract: Provided is a semiconductor device including a sequential circuit including a first transistor and a capacitor. The first transistor includes a semiconductor layer including indium, zinc, and oxygen to form a channel formation region. A node electrically connected to a source or a drain of the first transistor and a capacitor becomes a floating state when the first transistor turns off, so that a potential of the node can be maintained for a long period. A power-gating control circuit may be provided to control supply of power supply potential to the sequential circuit. The potential of the node still can be maintained while supply of the power supply potential is stopped.

公开(公告)号：US09471182B2

公开(公告)日：2016-10-18

申请号：US14827567

申请日：2015-08-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama ,  Shunpei Yamazaki

IPC: H01L27/146 ,  G06F3/042 ,  H01L31/105 ,  H01L27/144 ,  G02F1/1333

CPC classification number: G06F3/042 ,  G02F1/13338 ,  H01L27/1446 ,  H01L27/1461 ,  H01L27/14641 ,  H01L27/14678 ,  H01L31/105

Abstract: In a display portion of a liquid crystal display device, the dead space corresponding to a unit pixel is reduced while the aperture ratio of the unit pixel is increased. One amplifier circuit portion is shared by a plurality of unit pixels, so that the area of the amplifier circuit portion corresponding to the unit pixel is reduced and the aperture ratio of the unit pixel is increased. In addition, when the amplifier circuit portion is shared by a larger number of unit pixels, a photosensor circuit corresponding to the unit pixel can be prevented from increasing in area even with an increase in photosensitivity. Furthermore, an increase in the aperture ratio of the unit pixel results in a reduction in the power consumption of a backlight in a liquid crystal display device.

Abstract translation: 在液晶显示装置的显示部分中，与单位像素对应的死空间减小，同时单位像素的开口率增加。 一个放大器电路部分由多个单位像素共享，使得与单位像素相对应的放大器电路部分的面积减小，单位像素的开口率增加。 此外，当放大器电路部分被更多数量的单位像素共享时，即使随着光敏度的增加，也可以防止与单位像素相对应的光传感器电路的面积增加。 此外，单位像素的开口率的增加导致液晶显示装置中的背光的功耗的降低。

公开(公告)号：US09461126B2

公开(公告)日：2016-10-04

申请号：US14479673

申请日：2014-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei Yamazaki ,  Masahiro Katayama ,  Kenichi Okazaki ,  Jun Koyama

IPC: H03B1/00 ,  H03K3/00 ,  H01L29/26 ,  H03K19/096 ,  H03K3/356 ,  H03K3/037 ,  H03K5/15 ,  H03K19/0944

CPC classification number: H01L29/7869 ,  G11C19/28 ,  H01L27/1225 ,  H01L29/26 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/78648 ,  H01L29/78696 ,  H03K3/037 ,  H03K3/356121 ,  H03K5/15093 ,  H03K19/09443 ,  H03K19/096

Abstract: A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.

Abstract translation: 提供具有优异电特性（例如导通电流，场效应迁移率或频率特性）的晶体管。 晶体管包括包括沟道形成区域，第一栅极电极，第二栅极电极，源极电极和漏极电极的氧化物半导体层。 氧化物半导体层位于第一栅极电极和第二栅极电极之间。 氧化物半导体层具有与源电极和漏电极接触的一对侧面，并且包括被第一栅极电极和第二栅电极围绕的区域，其间没有源电极和漏电极。

公开(公告)号：US09431431B2

公开(公告)日：2016-08-30

申请号：US14070976

申请日：2013-11-04

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

IPC: H01L27/14 ,  H01L27/12 ,  G02F1/1345 ,  H01L29/45 ,  H01L29/786 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

Abstract: This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

公开(公告)号：US09412762B2

公开(公告)日：2016-08-09

申请号：US14445370

申请日：2014-07-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun Koyama ,  Kei Takahashi

IPC: H01L27/12 ,  H01L29/786 ,  H03K7/08 ,  H02M3/156

CPC classification number: H02M3/156 ,  G09G3/2092 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696 ,  H02M3/33523 ,  H02M3/33553 ,  H03K7/08

Abstract: A DC-DC converter with low power consumption and high power conversion efficiency is provided. The DC-DC converter includes a first transistor and a control circuit. The control circuit includes an operational amplifier generating a signal that controls switching of the first transistor, a bias circuit generating a bias potential supplied to the operational amplifier, and a holding circuit holding the bias potential. The holding circuit includes a second transistor and a capacitor to which the bias potential is supplied. The first transistor and the second transistor include a first oxide semiconductor film and a second oxide semiconductor film, respectively. The first oxide semiconductor film and the second oxide semiconductor film each contain In, M (M is Ga, Y, Zr, La, Ce, or Nd), and Zn. The atomic ratio of In to M in the first oxide semiconductor film is higher than that in the second oxide semiconductor film.

Abstract translation: 提供具有低功耗和高功率转换效率的DC-DC转换器。 DC-DC转换器包括第一晶体管和控制电路。 控制电路包括运算放大器，其产生控制第一晶体管的切换的信号，产生施加到运算放大器的偏置电位的偏置电路和保持偏置电位的保持电路。 保持电路包括第二晶体管和提供偏置电位的电容器。 第一晶体管和第二晶体管分别包括第一氧化物半导体膜和第二氧化物半导体膜。 第一氧化物半导体膜和第二氧化物半导体膜各自含有In，M（M为Ga，Y，Zr，La，Ce或Nd）和Zn。 第一氧化物半导体膜中的In与M的原子比高于第二氧化物半导体膜中的原子比。

公开(公告)号：US09390665B2

公开(公告)日：2016-07-12

申请号：US14085952

申请日：2013-11-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun Koyama

IPC: G09G3/36 ,  G06F3/041 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/136

CPC classification number: G09G3/3614 ,  G02F1/13338 ,  G02F1/1368 ,  G02F2001/13606 ,  G06F3/0412 ,  G06F3/044 ,  G06F2203/04103 ,  G09G3/3648 ,  G09G2320/0219 ,  G09G2320/0247 ,  G09G2320/103 ,  G09G2330/021 ,  H01L29/7869 ,  H01L29/78696

Abstract: A novel highly reliable display device is provided. Further, a novel display device capable of displaying images with less flicker is provided. Further, a display device capable of displaying eye-friendly still images is provided. The display device includes a feedthrough correction circuit which corrects a primary image signal. The feedthrough correction circuit corrects the primary image signal to compensate predicted feedthrough.

Abstract translation: 提供了一种新颖的高度可靠的显示装置。 此外，提供了能够显示具有较少闪烁的图像的新型显示装置。 此外，提供了能够显示适合眼睛的静止图像的显示装置。 显示装置包括校正主图像信号的馈通校正电路。 馈通校正电路校正主图像信号以补偿预测馈通。

公开(公告)号：US09378776B2

公开(公告)日：2016-06-28

申请号：US14625786

申请日：2015-02-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama

IPC: G11C5/06 ,  G11C11/418 ,  G11C5/10 ,  G11C8/16 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC classification number: G11C5/063 ,  G11C5/10 ,  G11C8/16 ,  G11C11/40 ,  G11C11/408 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/418

Abstract: A semiconductor device with a small cell area and excellent data read/write capability is achieved. In the semiconductor device, a wiring for writing data is provided, and a first transistor with a low off-state current is turned on to supply data to a gate of a second transistor and is turned off so that electric charge corresponding to data is retained. Moreover, a wiring for reading data is provided, and a third transistor is turned on so that data is read out in accordance with the on/off state of the second transistor retaining the electric charge. With this configuration, data write and data read are achieved in the same cycle.

Abstract translation: 实现了具有小单元面积和优异的数据读/写能力的半导体器件。 在半导体装置中，设置用于写入数据的布线，并且导通具有低截止电流的第一晶体管，以将数据提供给第二晶体管的栅极，并将其关闭，使得与数据相对应的电荷被保留 。 此外，提供用于读取数据的布线，并且第三晶体管导通，使得根据保持电荷的第二晶体管的导通/截止状态读出数据。 通过这种配置，数据写入和数据读取可以在同一周期内实现。

公开(公告)号：US09374048B2

公开(公告)日：2016-06-21

申请号：US14462007

申请日：2014-08-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Jun Koyama ,  Kei Takahashi ,  Shunpei Yamazaki

IPC: H03K3/012 ,  H03F3/04 ,  H03F3/45 ,  H03F1/02 ,  H03F3/193

CPC classification number: H03F1/0205 ,  H03F1/0261 ,  H03F3/193 ,  H03F3/45183 ,  H03F2200/555

Abstract: A power switch 307a is provided between a bias generation circuit 301 and a high potential power source, or a power switch 307b is provided between the bias generation circuit 301 and a low potential power source. A bias potential Vb output from the bias generation circuit 301 is held by a potential holding circuit 300. The bias potential Vb held by the potential holding circuit 300 is input to a bias generation circuit 301a, and a bias potential Vb2 output from the bias generation circuit 301a on which an input signal IN is superimposed is input to an amplifier circuit 302. The potential holding circuit 300 is constituted of a capacitor 306 and a switch 305 formed of, for example, a transistor with a low off-state current that is formed using a wide band gap oxide semiconductor. Structures other than the above structure are claimed.

Abstract translation: 电源开关307a设置在偏置产生电路301和高电位电源之间，或者电源开关307b设置在偏置产生电路301和低电位电源之间。 从电位保持电路300保持从偏置生成电路301输出的偏置电位Vb。由电位保持电路300保持的偏置电位Vb被输入到偏置生成电路301a，从偏置生成电路输出的偏置电位Vb2 其上叠加有输入信号IN的电路301a被输入到放大器电路302.电位保持电路300由电容器306和例如由例如具有低截止电流的晶体管形成的开关305构成， 使用宽带隙氧化物半导体形成。 要求保护除上述结构以外的结构。

公开(公告)号：US09373643B2

公开(公告)日：2016-06-21

申请号：US14541269

申请日：2014-11-14

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H04B1/28 ,  H04B1/38 ,  H01L27/12 ,  H01L27/06 ,  H01L29/786 ,  H04B1/40 ,  G06K19/077 ,  H01L29/10

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.