公开(公告)号：US20130320291A1

公开(公告)日：2013-12-05

申请号：US13961479

申请日：2013-08-07

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Scott E. Sills ,  Whitney L. West ,  Rob B. Goodwin ,  Nishant Sinha

IPC: H01L45/00

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the first conductive material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 形成用于半导体结构和存储单元的导电元件例如互连和电极的方法。 所述方法包括在至少一个开口的一部分中形成第一导电材料和第二导电材料，所述第二导电材料包括银，并且执行抛光工艺以用至少一个第一和第二导电材料填充所述至少一个开口。 可以进行退火处理以形成银和第一导电材料的混合物或合金。 该方法能够形成具有减小的尺寸（例如，小于约20nm）的含银导电元件。 所得的导电元件具有所需的电阻率。 所述方法可以用于例如形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了一种半导体结构和包括这种导电结构的存储单元。

公开(公告)号：US20130309820A1

公开(公告)日：2013-11-21

申请号：US13953450

申请日：2013-07-29

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak ,  Werner Juengling

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/4236 ,  H01L29/7841

Abstract: Floating body cell structures including an array of floating body cells disposed on a back gate and source regions and drain regions of the floating body cells spaced apart from the back gate. The floating body cells may each include a volume of semiconductive material having a channel region extending between pillars, which may be separated by a void, such as a U-shaped trench. The floating body cells of the array may be electrically coupled to another gate, which may be disposed on sidewalls of the volume of semiconductive material or within the void therein. Methods of forming the floating body cell devices are also disclosed.

公开(公告)号：US20130295726A1

公开(公告)日：2013-11-07

申请号：US13939082

申请日：2013-07-10

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Janos Fucsko

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/228 ,  H01L27/24

Abstract: Some embodiments include methods of forming memory arrays. A stack of semiconductor material plates may be patterned to subdivide the plates into pieces. Electrically conductive tiers may be formed along sidewall edges of the pieces. The pieces may then be patterned into an array of wires, with the array having vertical columns and horizontal rows. Individual wires may have first ends joining to the electrically conductive tiers, may have second ends in opposing relation to the first ends, and may have intermediate regions between the first and second ends. Gate material may be formed along the intermediate regions. Memory cell structures may be formed at the second ends of the wires. A plurality of vertically-extending electrical interconnects may be connected to the wires through the memory cell structures, with individual vertically-extending electrical interconnects being along individual columns of the array. Some embodiments include memory arrays incorporated into integrated circuitry.

Abstract translation: 一些实施例包括形成存储器阵列的方法。 一叠半导体材料板可以被图案化以将该板细分成多个。 导电层可以沿着片的侧壁边缘形成。 然后将这些片材图案化成线阵列，阵列具有垂直列和水平行。 单独的线可以具有连接到导电层的第一端，可以具有与第一端相对的第二端，并且可以在第一端和第二端之间具有中间区域。 栅极材料可以沿着中间区域形成。 存储单元结构可以形成在电线的第二端。 多个垂直延伸的电互连可以通过存储单元结构连接到导线，其中各个垂直延伸的电互连沿阵列的各个列。 一些实施例包括并入到集成电路中的存储器阵列。

公开(公告)号：US20130235650A1

公开(公告)日：2013-09-12

申请号：US13850348

申请日：2013-03-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gurtej S. Sandhu ,  Sanh D. Tang

IPC: G11C13/00

CPC classification number: G11C13/0002 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C8/12 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/004 ,  G11C2213/71 ,  H01L27/0688 ,  H01L27/101

Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

公开(公告)号：US20130230959A1

公开(公告)日：2013-09-05

申请号：US13861082

申请日：2013-04-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sanh D. Tang ,  Michael P. Violette ,  Robert Burke

IPC: H01L29/78

CPC classification number: H01L29/7833 ,  G06K19/0723 ,  G06K19/0726 ,  G06K19/07771 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76264 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.

Abstract translation: 在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。 开口具有包括半导体材料的基底。 在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。 绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。 在开口内的绝缘材料的开口内形成半导电源极/漏极材料。 半导体源极/漏极材料可操作地提供晶体管栅极。 考虑了其他方面和实现。

公开(公告)号：US12219758B2

公开(公告)日：2025-02-04

申请号：US18428325

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240186234A1

公开(公告)日：2024-06-06

申请号：US18441767

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Roger W. Lindsay ,  Krishna K. Parat

IPC: H01L23/52 ,  G11C13/00 ,  H01L23/528 ,  H01L27/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35 ,  H10B63/00 ,  H10N70/00

CPC classification number: H01L23/52 ,  G11C13/0007 ,  H01L23/528 ,  H01L27/10 ,  H01L27/101 ,  H10B41/27 ,  H10B43/27 ,  H10B43/35 ,  H10B63/845 ,  H10N70/8822 ,  H10N70/8825 ,  H10N70/8828 ,  H10N70/8833 ,  H10N70/8836 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L2924/0002 ,  H10B41/35 ,  H10N70/882 ,  H10N70/883

Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The features extend horizontally though a primary portion of the stack with at least some of the features extending farther in the horizontal direction in an end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the openings. Other aspects and implementations are disclosed.

公开(公告)号：US11700730B2

公开(公告)日：2023-07-11

申请号：US17129146

申请日：2020-12-21

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/11582 ,  H01L27/11551 ,  H10B43/27 ,  H01L21/28 ,  H01L27/06 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/00 ,  H01L21/768 ,  G11C13/00 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L23/528 ,  H10N70/20

CPC classification number: H10B43/27 ,  G11C13/004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L21/76838 ,  H01L23/528 ,  H01L27/0688 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926 ,  H10B41/10 ,  H10B41/20 ,  H10B41/27 ,  H10B41/50 ,  H10B43/10 ,  H10B43/20 ,  H10B43/50 ,  H10B63/34 ,  H10B63/845 ,  G11C2213/71 ,  H10N70/231

Abstract: Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

公开(公告)号：US11600535B2

公开(公告)日：2023-03-07

申请号：US16868133

申请日：2020-05-06

Applicant: Micron Technology, inc.

Inventor： Litao Yang ,  Srinivas Pulugurtha ,  Yunfei Gao ,  Sanh D. Tang ,  Haitao Liu

IPC: H01L27/00 ,  H01L21/84 ,  H01L21/265 ,  H01L29/78 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11581324B2

公开(公告)日：2023-02-14

申请号：US16813332

申请日：2020-03-09

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  John K. Zahurak

IPC: H01L27/11556 ,  H01L29/792 ,  H01L27/11582 ,  H01L27/11578 ,  H01L21/28 ,  H01L27/11524 ,  H01L27/11521 ,  H01L29/04 ,  H01L29/167 ,  H01L29/49 ,  H01L29/788

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.