公开(公告)号：US20170337974A1

公开(公告)日：2017-11-23

申请号：US15673218

申请日：2017-08-09

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/26 ,  G11C16/10 ,  G11C7/00 ,  G11C16/04 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/26 ,  G11C7/00 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459

Abstract: Embodiments are provided that include a method including providing a first voltage to a selected memory cell and providing a second voltage to the selected memory cell during an operation. The first voltage is greater in magnitude than the second voltage and the first voltage is applied for a shorter duration than the second voltage. The method also includes determining a state of the memory cell after providing the first voltage and the second voltage.

公开(公告)号：US09786334B2

公开(公告)日：2017-10-10

申请号：US15164400

申请日：2016-05-25

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11529 ,  G11C16/26 ,  G11C5/02 ,  G11C7/12 ,  G11C7/22 ,  G11C16/16 ,  G11C16/08

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US09779819B1

公开(公告)日：2017-10-03

申请号：US15191786

申请日：2016-06-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Qiang Tang ,  Ramin Ghodsi ,  Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3459

Abstract: In an example, a programming method includes applying a program voltage to a selected access line commonly connected to a first memory cell of a first string of series-connected memory cells and to a second memory cell of a second string of series-connected memory cells while a data line is electrically connected to the first memory cell and electrically disconnected from the second memory cell, and while continuing to apply the program voltage to the selected access line, electrically disconnecting the data line from the first memory cell and subsequently electrically connecting the data line to the second memory cell.

公开(公告)号：US09779791B2

公开(公告)日：2017-10-03

申请号：US14542244

申请日：2014-11-14

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C8/10 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C11/408 ,  G11C7/00 ,  G11C13/00 ,  G11C8/18

CPC classification number: G11C8/10 ,  G11C7/00 ,  G11C7/02 ,  G11C8/12 ,  G11C8/16 ,  G11C8/18 ,  G11C11/4087 ,  G11C13/0004 ,  G11C13/003

Abstract: Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

公开(公告)号：US09721960B2

公开(公告)日：2017-08-01

申请号：US14656980

申请日：2015-03-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/11519 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11556

CPC classification number: H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include an apparatus having semiconductor pillars in a modified hexagonal packing arrangement. The modified hexagonal packing arrangement includes a repeating pattern having at least portions of 7 different pillars. Each of the 7 different pillars is immediately adjacent to six neighboring pillars. A distance to two of the six neighboring pillars is a short distance, ds; and a distance to four of the six neighboring pillars is a long distance, dl. Some embodiments include an apparatus having semiconductor pillars in a packing arrangement. The packing arrangement comprises alternating first and second rows, with pillars in the first rows being laterally offset relative to pillars in the second rows. A distance between neighboring pillars in a common row as one another is a short distance, ds, and a distance between neighboring pillars that are not in common rows as one another is a long distance, dl.

公开(公告)号：US20170110198A1

公开(公告)日：2017-04-20

申请号：US15393719

申请日：2016-12-29

Applicant: Micron Technology, Inc.

Inventor： Han Zhao ,  Akira Goda ,  Krishna K. Parat ,  Aurelio Giancarlo Mauri ,  Haitao Liu ,  Toru Tanzawa ,  Shigekazu Yamada ,  Koji Sakui

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/04

CPC classification number: G11C16/3459 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3445 ,  G11C2213/71

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatus and a data line coupled to the memory cell string. The memory cell string includes a pillar body associated with the memory cells. At least one of such apparatus can include a module configured to store information in a memory cell among memory cells and/or to determine a value of information stored in a memory cell among memory cells. The module can also be configured to apply a voltage having a positive value to the data line and/or a source to control a potential of the body. Other embodiments are described.

公开(公告)号：US20160357441A1

公开(公告)日：2016-12-08

申请号：US15244163

申请日：2016-08-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F3/06 ,  G06F12/14 ,  G06F12/06

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Abstract translation: 操作存储器的方法包括执行存储器访问操作，在停止存储器访问操作之前获得对应于后续存储器访问操作的地址，停止存储器访问操作，在用于存储器存取操作的存取线之间共享电荷和存取行 用于随后的存储器访问操作，并且执行后续存储器存取操作。

公开(公告)号：US09412451B2

公开(公告)日：2016-08-09

申请号：US14509953

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa ,  Aaron Yip

IPC: G11C16/04 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.

Abstract translation: 描述了用于降低电容负载的装置和方法。 示例性装置可以包括存储器块的多个存储器子块。 多个字线可以与多个子块相关联。 字线可以进一步与子块内的多个字符串相关联。 字线的子集可以是虚拟字线。 虚拟字线的单元可以被编程为多个状态。 可以将状态配置为在某些存储器操作期间停用和/或浮动子块中未选择的字符串。

公开(公告)号：US09368216B2

公开(公告)日：2016-06-14

申请号：US14813711

申请日：2015-07-30

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C16/10 ,  G11C5/06 ,  H01L27/115 ,  G11C16/26 ,  G11C5/02 ,  G11C16/16

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C7/12 ,  G11C7/222 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11551

Abstract: Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

公开(公告)号：US20160163727A1

公开(公告)日：2016-06-09

申请号：US15043921

申请日：2016-02-15

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115 ,  H01L29/04 ,  H01L29/16

CPC classification number: H01L27/11556 ,  G11C16/04 ,  G11C16/0408 ,  H01L21/04 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.