公开(公告)号：US20170250262A1

公开(公告)日：2017-08-31

申请号：US15594757

申请日：2017-05-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L29/49 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US09698230B2

公开(公告)日：2017-07-04

申请号：US15283951

申请日：2016-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/70 ,  H01L29/417 ,  H01L29/08 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US09685537B1

公开(公告)日：2017-06-20

申请号：US15280521

申请日：2016-09-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Tenko Yamashita ,  Kangguo Cheng ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/41 ,  H01L21/336 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/423

CPC classification number: H01L29/66666 ,  H01L21/31051 ,  H01L21/31144 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7827 ,  H01L2029/7858

Abstract: A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, an impurity layer of n-type or p-type over the semiconductor substrate, a first hard mask layer over the semiconductor layer, a first dielectric layer over the first hard mask layer, a second hard mask layer over the first dielectric layer, a second dielectric layer over the second hard mask layer and a protective layer over the second dielectric layer. The method further includes patterning the second dielectric layer and protective layer, the patterning forming an opening therein, forming a wrap-around spacer on an inner sidewall of the opening, the forming leaving a smaller opening, forming a vertical channel, and setting a gate length of a wrap-around gate by removing an outer portion of the structure.

公开(公告)号：US20170154883A1

公开(公告)日：2017-06-01

申请号：US15181676

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/06 ,  H01L29/93 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

公开(公告)号：US20170154821A1

公开(公告)日：2017-06-01

申请号：US15291750

申请日：2016-10-12

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Junli Wang ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L29/93

CPC classification number: H01L27/0629 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/823431 ,  H01L27/0733 ,  H01L29/1083 ,  H01L29/66174 ,  H01L29/66537 ,  H01L29/6656 ,  H01L29/785 ,  H01L29/93

Abstract: A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second region. The finFET includes a first semiconductor fin that extends from an upper finFET surface thereof to the upper surface of the first region to define a first total fin height. The fin varactor includes a second semiconductor fin that extends from an upper varactor surface thereof to the upper surface of the second region to define a second total fin height that is different from the first total fin height of the finFET.

公开(公告)号：US20170140987A1

公开(公告)日：2017-05-18

申请号：US15254096

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/522

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US20170125284A1

公开(公告)日：2017-05-04

申请号：US15342440

申请日：2016-11-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/768 ,  H01L29/423 ,  H01L23/522 ,  H01L29/417 ,  H01L21/28 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US09640436B1

公开(公告)日：2017-05-02

申请号：US15254096

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

Inventor： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/70 ,  H01L21/768 ,  H01L23/522 ,  H01L29/66 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L29/41791 ,  H01L21/76224 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/535 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.

公开(公告)号：US20170117276A1

公开(公告)日：2017-04-27

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/6653 ,  H01L21/2018 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31053 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.

公开(公告)号：US09633911B2

公开(公告)日：2017-04-25

申请号：US14668482

申请日：2015-03-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Qing Liu ,  Nicolas Loubet ,  Scott Luning

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/845 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/4966

Abstract: A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.