公开(公告)号：US20020123195A1

公开(公告)日：2002-09-05

申请号：US10006778

申请日：2001-11-05

Applicant: STMicroelectronics S.r.I

Inventor： Ferruccio Frisina ,  Giuseppe Ferla ,  Salvatore Rinaudo

IPC: H01L021/336

CPC classification number: H01L29/7802 ,  H01L29/0847 ,  H01L29/66712

Abstract: A MOS-gated power device includes a plurality of elementary functional units, each elementary functional unit including a body region of a first conductivity type formed in a semiconductor material layer of a second conductivity type having a first resistivity value. Under each body region a respective lightly doped region of the second conductivity type is provided having a second resistivity value higher than the first resistivity value.

Abstract translation: MOS门控功率器件包括多个基本功能单元，每个基本功能单元包括形成在具有第一电阻率值的第二导电类型的半导体材料层中的第一导电类型的体区。 在每个体区下方提供具有高于第一电阻率值的第二电阻率值的第二导电类型的相应轻掺杂区。

公开(公告)号：US20020113247A1

公开(公告)日：2002-08-22

申请号：US10072817

申请日：2002-02-08

Applicant: STMicroelectronics S.r.I.

Inventor： Angelo Magri ,  Leonardo Fragapane

IPC: H01L029/76

CPC classification number: H01L24/06 ,  H01L23/49562 ,  H01L24/48 ,  H01L24/49 ,  H01L25/071 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01093 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A method of manufacturing an electronic structure, which structure comprises a first power device and a second unidirectional device, both integrated in the same protective package. The first device having at least first and second electrodes of the first device, with said first electrode of the first device being attached to the package. The second device having first and second electrodes of the second device, wherein the first electrode of the second device is superposed on the second electrode of the first device and connected electrically to the second electrode of the first device.

Abstract translation: 一种制造电子结构的方法，该结构包括集成在同一保护封装中的第一电力装置和第二单向装置。 所述第一装置具有所述第一装置的至少第一和第二电极，所述第一装置的所述第一电极附接到所述包装。 第二装置具有第二装置的第一和第二电极，其中第二装置的第一电极重叠在第一装置的第二电极上并与第一装置的第二电极电连接。

公开(公告)号：US20020070464A1

公开(公告)日：2002-06-13

申请号：US09997995

申请日：2001-11-30

Applicant: STMicroelectronics S.r.I.

Inventor： Giovanni Frezza

IPC: H01L023/29

CPC classification number: H01L21/565 ,  H01L2224/32245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/1815 ,  H01L2924/00

Abstract: A method for forming by molding a plastic protective package for an electronic integrated circuit that includes an electronic device activated from the outside of said protective package. The method includes: dispensing a covering layer of elastic material on a portion of said electronic device; shaping said covering layer to form a projecting portion from a surface of said electronic device; molding said electronic integrated circuit in said plastic protective package using a mold including at least a half-mold abutting against said projecting portion; and obtaining a hole or a window formed in alignment with said projecting portion in said protective package.

Abstract translation: 一种用于通过模制用于电子集成电路的塑料保护包装形成的方法，该电子集成电路包括从所述保护包装的外部激活的电子装置。 该方法包括：在所述电子设备的一部分上分配弹性材料的覆盖层; 成形所述覆盖层以从所述电子设备的表面形成突出部分; 使用包括至少半个模具抵靠所述突出部分的模具将所述电子集成电路模制在所述塑料保护包装中; 并且获得与所述保护包装中的所述突出部分对准形成的孔或窗口。

公开(公告)号：US20020057604A1

公开(公告)日：2002-05-16

申请号：US09953070

申请日：2001-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Osama Khouri ,  Alessandro Manstretta ,  Guido Torelli

IPC: G11C007/00

CPC classification number: G11C7/062 ,  G11C16/28 ,  G11C2207/063

Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving at the input thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, as well as at least one differential amplifier, connected at the input of the first and the second nodes and having an output terminal effective to provide a logic signal correlated to the selected cell information. The reading circuit also includes at least a first voltage-controlled discharge switch circuit connected at the input of the first node and to a voltage reference, a second voltage-controlled discharge switch circuit connected at the input of the second node and to the voltage reference, as well as a first and a second voltage comparator circuits receiving at the input thereof the first selected cell voltage and the second reference cell voltage. Moreover, advantageously according to the invention, the comparator circuits are effective to control the switch circuits.

Abstract translation: 一种用于连接到至少一个选定单元和至少一个参考单元的半导体非易失性存储器的读取电路，所述电路包括电流/电压转换电路，其在输入端接收流过选定单元的第一电流和流过所选单元的第二电流 所述参考单元并且分别在第一电路节点上提供第一选择的单元电压，并在第二节点上提供第二参考单元电压以及至少一个差分放大器，所述差分放大器连接在所述第一和第二节点的输入端，并且具有 输出端有效地提供与所选择的单元信息相关的逻辑信号。 读取电路还包括至少连接在第一节点的输入端和电压基准的第一压控放电开关电路，连接在第二节点的输入端的第二压控放电开关电路和电压基准 以及在其输入端接收第一选定单元电压和第二参考单元电压的第一和第二电压比较器电路。 此外，有利地根据本发明，比较器电路有效地控制开关电路。

公开(公告)号：US20020050627A1

公开(公告)日：2002-05-02

申请号：US10033508

申请日：2001-12-28

Applicant: STMicroelectronics S.r.I.

Inventor： Raffaele Zambrano

IPC: H01L029/00

CPC classification number: H01L27/11502 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/76877 ,  H01L27/0629 ,  H01L27/1085 ,  H01L28/55 ,  H01L28/60 ,  H01L28/75

Abstract: A contact structure for semiconductor devices which are integrated on a semiconductor layer is provided. The structure comprises at least one MOS device and at least one capacitor element where the contact is provided at an opening formed in an insulating layer which overlies at least in part the semiconductor layer. Further, the opening has its surface edges, walls and bottom coated with a metal layer and filled with an insulating layer.

Abstract translation: 提供集成在半导体层上的用于半导体器件的接触结构。 该结构包括至少一个MOS器件和至少一个电容器元件，其中触点设置在形成在至少部分半导体层的绝缘层中的开口处。 此外，开口具有其表面边缘，壁和底部涂覆有金属层并且填充有绝缘层。

公开(公告)号：US20020041729A1

公开(公告)日：2002-04-11

申请号：US09925847

申请日：2001-08-08

Applicant: STMicroelectronics S.r.I.

Inventor： Ubaldo Mastromatteo ,  Bruno Murari

IPC: G02B006/26 ,  G02B006/35

CPC classification number: H02N1/004 ,  B81B3/0051 ,  B81B2201/045 ,  B81B2203/051 ,  B81B2203/058 ,  F16H21/02 ,  G02B26/0841 ,  G02B26/0866

Abstract: A microelectromechanical structure, usable in an optical switch for directing a light beam towards one of two light guide elements, including: a mirror element, rotatably movable; an actuator, which can translate; and a motion conversion assembly, arranged between the mirror element and the actuator. The motion conversion assembly includes a projection integral with the mirror element and elastic engagement elements integral with the actuator and elastically loaded towards the projection. The elastic engagement elements are formed by metal plates fixed to the actuator at one of their ends and engaging the projection with an abutting edge countershaped with respect to the projection.

公开(公告)号：US20020035679A1

公开(公告)日：2002-03-21

申请号：US09998568

申请日：2001-11-16

Applicant: STMicroelectronics S.r.I.

Inventor： Francesco Pappalardo ,  Davide Tesi ,  Francesco Nino Mammoliti ,  Francesco Bombaci

IPC: G06F009/00

CPC classification number: G06F9/30181 ,  G06F9/30003 ,  G06F9/30145

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract translation: 处理器设置有一组通常由操作部分和操作数部分形成的指令。 对于至少一个指令，操作数部分表示处理器的操作控制信号。 以这种方式，可以实现该组指令的扩展，以便根据用户自己的要求定制指令集。 因此，处理器控制单元应该能够在接收到一个这样的指令时将其输出耦合到其输入，从而在没有解释的情况下传送这样的内部操作控制信号。

公开(公告)号：US20020001153A1

公开(公告)日：2002-01-03

申请号：US09812715

申请日：2001-03-20

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Maiocchi

IPC: G11B015/46

CPC classification number: G11B19/20 ,  G11B19/28 ,  G11B21/02

Abstract: The device is for driving and controlling a rotation motor and a voice coil motor for a hard disk drive system that includes a disk and an arm carrying a read/write head to be positioned with respect thereto. A duty-cycle control loop including a current sensing circuit is connected to the voice coil motor, and an arm position control loop including a speed detection circuit is also connected to the voice coil motor. The duty-cycle control loop and the arm position control loop are digitally implemented by a DSP as a function of digital data representing a first analog signal generated by the current sensing circuit representative of current conducting in a winding of the voice coil motor, and a second analog signal generated by the speed detection circuit representative of an instant speed of the voice coil motor.

Abstract translation: 该装置用于驱动和控制用于硬盘驱动系统的旋转电动机和音圈电动机，该系统包括盘和携带读/写头相对于其定位的臂。 包括电流感测电路的占空比控制回路连接到音圈电动机，并且包括速度检测电路的臂位置控制回路也连接到音圈电动机。 占空比控制回路和臂位置控制回路由DSP作为数字数据数字地实现，该数字数据表示由代表在线圈电动机的绕组中的电流传导的电流感测电路产生的第一模拟信号，以及 由速度检测电路产生的代表音圈电机瞬时速度的第二模拟信号。

公开(公告)号：US20010024131A1

公开(公告)日：2001-09-27

申请号：US09745286

申请日：2000-12-21

Applicant: STMicroelectronics S.r.I

Inventor： Raffaele Solimene

IPC: H03K005/19

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C16/08 ,  G11C16/32

Abstract: The selection/deselection circuit is for non-volatile memory word lines having a decoding line connected between a supply voltage and ground, and including a series of decoding transistors of the same conductivity controlled by respective selection signals and at least a load transistor whose conductivity is opposite to the conductivity of the decoding transistors in series with the series of transistors and biased by a control voltage. The load transistor produces an activating or deactivating voltage of a memory word line, and a circuit for controlling the load transistor is provided. Such an auxiliary control circuit includes a sensing element in series with the decoding transistors and the load transistor for producing a sensing signal switching between a first value when only one memory line is actually selected and a second value when multiple memory word lines appear to be simultaneously selected. Also, an inverter receives the sensing signal and outputs a first signal. A high pass filter receives the first signal and produces a control transient voltage for transitorily bringing the load transistor to a state of full conduction when the sensing signal switches from the first value to the second value.

Abstract translation: 选择/取消选择电路是用于具有连接在电源电压和地之间的解码线的非易失性存储字线，并且包括由各个选择信号控制的相同电导率的一系列解码晶体管和至少一个负载晶体管，其导电性为 与与晶体管系列串联的解码晶体管的导电性相反，并由控制电压偏置。 负载晶体管产生存储字线的激活或去激活电压，并且提供用于控制负载晶体管的电路。 这样的辅助控制电路包括与解码晶体管和负载晶体管串联的感测元件，用于当仅实际选择一个存储器线路时产生在第一值之间切换的感测信号，并且当多个存储器字线似乎同时显示时的第二值 选择。 此外，逆变器接收感测信号并输出​​第一信号。 当检测信号从第一值切换到第二值时，高通滤波器接收第一信号并产生控制瞬态电压，用于将负载晶体管暂时地导通到全导通状态。

公开(公告)号：US20010016379A1

公开(公告)日：2001-08-23

申请号：US09750449

申请日：2000-12-28

Applicant: STMicroelectronics S.r.I.

Inventor： Nicola Nastasi ,  Dorotea Arcidiacono ,  Stefano Mazzali

IPC: H01L021/8238

CPC classification number: H01L27/11521

Abstract: A method is provided for manufacturing electronic non-volatile memory devices on a semiconductor substrate including a matrix of memory cells having floating gate regions formed on respective active areas and an oxide layer separating the active areas. The method may include forming sidewalls of the floating gate regions that are slanted with respect to a surface of the semiconductor substrate, forming a trench in the oxide layer following the formation of the floating gate regions, and forming a plug of polycrystalline silicon in the trench. The slanted sidewalls of the floating gate regions provide a lead-in for the formation of upper layers.

Abstract translation: 提供了一种用于在半导体衬底上制造电子非易失性存储器件的方法，该半导体衬底包括具有形成在各自的有源区上的浮动栅极区域和分离有源区域的氧化物层的存储器单元的矩阵。 该方法可以包括形成相对于半导体衬底的表面倾斜的浮动栅极区域的侧壁，在形成浮动栅极区域之后在氧化物层中形成沟槽，以及在沟槽中形成多晶硅插塞 。 浮动栅极区域的倾斜侧壁提供用于形成上层的引入。