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    TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS
    261.
    发明申请
    TECHNIQUES FOR STORING DATA AND TAGS IN DIFFERENT MEMORY ARRAYS 审中-公开

    公开(公告)号：US20170168950A1

    公开(公告)日：2017-06-15

    申请号：US15389402

    申请日：2016-12-22

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G06F12/0895 ,  G11C8/06

    CPC classification number: G06F12/0895 ,  G06F12/0802 ,  G06F12/0851 ,  G06F12/1027 ,  G06F2212/1044 ,  G11C8/06

    Abstract: A memory controller includes logic circuitry to generate a first data address identifying a location in a first external memory array for storing first data, a first tag address identifying a location in a second external memory array for storing a first tag, a second data address identifying a location in the second external memory array for storing second data, and a second tag address identifying a location in the first external memory array for storing a second tag. The memory controller includes an interface that transfers the first data address and the first tag address for a first set of memory operations in the first and the second external memory arrays. The interface transfers the second data address and the second tag address for a second set of memory operations in the first and the second external memory arrays.

    MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION
    266.
    发明申请
    MEMORY CONTROLLER WITH CLOCK-TO-STROBE SKEW COMPENSATION 有权
    内存控制器，具有时钟对条纹补偿

    公开(公告)号：US20170040047A1

    公开(公告)日：2017-02-09

    申请号：US15242425

    申请日：2016-08-19

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C11/4076 ,  G06F13/42 ,  G06F13/16 ,  G11C11/409 ,  G06F1/10

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

    Abstract translation: 时钟信号通过时钟信号线发送到第一和第二集成电路（IC）组件，该时钟信号在第一IC组件处具有第一到达时间，而在第二IC组件处具有第二较晚的到达时间。 在对应于时钟信号的转变的各个时刻，写入命令被发送到要被这些分量采样的第一和第二IC组件，并且与写命令相关联地将写数据发送到第一和第二IC组件。 第一和第二选通信号分别被发送到第一和第二IC组件，以便在这些组件中对第一和第二写入数据进行时间接收。 从多个相位偏移定时信号中选择第一和第二选通信号，以补偿时钟信号与第一和第二选通信号之间的各自的定时偏差。

    Low-power source-synchronous signaling
    267.
    发明授权
    Low-power source-synchronous signaling 有权
    低功耗源同步信号

    公开(公告)号：US09536589B2

    公开(公告)日：2017-01-03

    申请号：US14445014

    申请日：2014-07-28

    Applicant: Rambus Inc.

    Inventor： Jared L. Zerbe ,  Frederick A. Ware

    IPC: G06F1/04 ,  G11C11/4076 ,  G06F13/42 ,  G11C7/22 ,  G11C7/04 ,  G11C7/10 ,  G11C29/02 ,  H04L7/00

    CPC classification number: G11C11/4076 ,  G06F1/04 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254 ,  H04L7/0008 ,  Y02D10/14 ,  Y02D10/151

    Abstract: A method of operating a memory controller is disclosed. The method includes transmitting data signals to a memory device over each one of at least two parallel data links. A timing signal is sent to the memory device on a first dedicated link. The timing signal has a fixed phase relationship with the data signals. A data strobe signal is driven to the memory device on a second dedicated link. Phase information is received from the memory device. The phase information being generated internal to the memory device and based on a comparison between the timing signal and a version of the data strobe signal internally distributed within the memory device. A phase of the data strobe signal is adjusted relative to the timing signal based on the received phase information.

    Abstract translation: 公开了一种操作存储器控制器的方法。 该方法包括通过至少两个并行数据链路中的每一个将数据信号发送到存储器设备。 在第一专用链路上将定时信号发送到存储设备。 定时信号与数据信号具有固定的相位关系。 数据选通信号被驱动到第二专用链路上的存储器件。 从存储器件接收相位信息。 所述相位信息在存储器件内部产生，并且基于定时信号与内部分布在存储器件内的数据选通信号的版本之间的比较。 基于接收的相位信息，相对于定时信号调整数据选通信号的相位。

    Integrated circute with multiple request ports and link calibration support
    268.
    发明申请
    Integrated circute with multiple request ports and link calibration support 有权
    具有多个请求端口和链路校准支持的集成循环

    公开(公告)号：US20160351234A1

    公开(公告)日：2016-12-01

    申请号：US15169331

    申请日：2016-05-31

    Applicant: Rambus Inc.

    Inventor： Richard E. Perego ,  Frederick A. Ware

    IPC: G11C7/10 ,  G06F13/16

    CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

    Abstract: A memory system includes a memory controller with multiple command/address ports and a memory device having corresponding request ports. The memory controller issues commands to memory device to cause the memory device to “loop-back” signals conveyed to memory device over one of the command/address ports via a bidirectional data link; these signals can be deterministic test patterns. The memory controller compares the returned information with the originally transmitted patterns to perform calibration. In one embodiment, because the return links are already calibrated, errors can be attributed to issues in the forward links; the memory controller then adjusts timing of the forward links to minimize the errors.

    Abstract translation: 存储器系统包括具有多个命令/地址端口的存储器控​​制器和具有相应请求端口的存储器件。 存储器控制器向存储器件发出命令以使存储器件通过双向数据链路“循环”传送到存储器件之一的命令/地址端口之一的信号; 这些信号可以是确定性的测试模式。 存储器控制器将返回的信息与原始传输的模式进行比较以执行校准。 在一个实施例中，由于返回链路已被校准，错误可归因于前向链路中的问题; 存储器控制器然后调整前向链路的定时以使误差最小化。

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