公开(公告)号：US09431090B2

公开(公告)日：2016-08-30

申请号：US14669919

申请日：2015-03-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/00 ,  G11C11/4076 ,  G06F13/16 ,  G11C29/02 ,  G11C29/50 ,  G11C11/406 ,  G11C11/409 ,  G11C7/22 ,  G11C7/10 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/40615 ,  G11C11/409 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: A memory system includes a memory controller that writes data to and reads data from a memory device. A write data strobe accompanying the write data indicates to the memory device when the write data is valid, whereas a read strobe accompanying data from the memory device indicates to the memory controller when the read data is valid. The memory controller adaptively controls the phase of the write data strobe to compensate for timing drift at the memory device. The memory controller uses read signals as a measure of the drift.

公开(公告)号：US20160232953A1

公开(公告)日：2016-08-11

申请号：US15017415

申请日：2016-02-05

Applicant: Rambus Inc.

Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

IPC: G11C7/22 ,  G11C7/02

CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

公开(公告)号：US09411678B1

公开(公告)日：2016-08-09

申请号：US13828828

申请日：2013-03-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Ely Tsern ,  Thomas Vogelsang ,  Wayne Ellis

IPC: H03M13/00 ,  G06F11/10

CPC classification number: G06F11/1008

Abstract: A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

Abstract translation: 一种在存储器件中的操作方法，包括将数据存储在存储器件中的第一组存储位置中，将与存储的数据相关联的错误信息存储在存储器件中的第二组存储位置中，并且选择性地评估误差信息 基于错误使能位的状态，基于对第一组存储位置的最近访问是否涉及部分访问的状态。

公开(公告)号：US09378787B2

公开(公告)日：2016-06-28

申请号：US14305799

申请日：2014-06-16

Applicant: Rambus Inc.

Inventor： Richard E. Perego ,  Frederick A. Ware

IPC: G06F13/16 ,  G11C7/10 ,  G11C5/06

CPC classification number: G11C7/1072 ,  G06F13/1678 ,  G06F13/1684 ,  G06F13/1694 ,  G11C5/06 ,  G11C7/1045 ,  G11C7/1075

Abstract: A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.

Abstract translation: 存储器系统包括具有多个存储器 - 控制器块的存储器控​​制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。 请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。 所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。 每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

公开(公告)号：US20160172271A1

公开(公告)日：2016-06-16

申请号：US15019867

申请日：2016-02-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Thomas Vogelsang

IPC: H01L23/48 ,  G06F3/06

CPC classification number: H01L23/481 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F2213/0038 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2225/06544 ,  H01L2924/014

Abstract: An integrated circuit die includes conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof. The integrated circuit also includes a core circuit located outside the contiguous region. The core circuit is coupled to at least one of the connection sites.

公开(公告)号：US09362002B2

公开(公告)日：2016-06-07

申请号：US14858888

申请日：2015-09-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C11/34 ,  G11C17/18 ,  G11C5/04 ,  H01L25/065 ,  G11C11/4096 ,  G11C17/16 ,  H01L25/18 ,  H01L23/00

CPC classification number: G11C11/4093 ,  G11C5/04 ,  G11C11/4096 ,  G11C17/16 ,  G11C17/18 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/08148 ,  H01L2224/8013 ,  H01L2224/80132 ,  H01L2224/80897 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00

Abstract: A stacked semiconductor device is disclosed that includes a plurality of semiconductor dies. Each die has oppositely disposed first and second surfaces, with pads formed on each of the surfaces. A plurality of through-vias connect respective pads on the first surface to respective pads on the second surface. The through-vias include a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of through-vias not coupled to I/O circuitry on the semiconductor die. The plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second one of the plurality of semiconductor dies.

公开(公告)号：US20160147281A1

公开(公告)日：2016-05-26

申请号：US14951150

申请日：2015-11-24

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/32 ,  G06F3/06

CPC classification number: G06F1/3237 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673 ,  G06F9/3836 ,  G06F12/0857 ,  G06F13/1689 ,  G06F13/36 ,  G06F2201/88 ,  G11C7/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/2254 ,  Y02D10/14

Abstract: In an integrated circuit device that outputs data values during respective transmit intervals defined by transitions of a transmit clock, the phase of the transmit clock is shifted by half a transmit interval to enable a timing calibration operation. Thereafter, a sequence of data values is transmitted to another integrated circuit device in response to the phase-shifted transmit clock and a samples of the sequence of data values are received from the other integrated circuit device. The received samples are compared with the sequence of data values to determine a phase update value, including comparing at least one received sample with two adjacent data values within the sequence of data values, and the phase of the transmit clock is incrementally advanced or retarded according to the phase update value.

Abstract translation: 在由发送时钟的转变定义的各个发送间隔期间输出数据值的集成电路装置中，发送时钟的相位偏移了发送间隔的一半，以实现定时校准操作。 此后，响应于相移发送时钟，将数据值序列发送到另一集成电路装置，并且从另一集成电路装置接收数据值序列的采样。 将接收到的采样与数据值序列进行比较，以确定相位更新值，包括将至少一个接收到的采样与数据值序列中的两个相邻数据值进行比较，并且传输时钟的相位按照 到相位更新值。

公开(公告)号：US09311976B2

公开(公告)日：2016-04-12

申请号：US14523922

申请日：2014-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

IPC: G11C7/00 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  G06F13/40 ,  G11C5/06 ,  G11C29/02 ,  G11C29/50 ,  G11C8/18 ,  G06F1/10 ,  G11C11/4076 ,  G11C11/409 ,  G11C7/04

CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

Abstract: A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Abstract translation: 具有集成电路（IC）组件，终端结构，地址/控制信号路径，时钟信号路径，多个数据信号路径和多个选通信号路径的存储模块。 选通信号路径和数据信号路径耦合到相应的IC组件，并且地址/控制信号路径和时钟信号路径共同耦合到所有IC组件。 地址/控制信号路径沿着IC组件延伸到终端结构，使得朝向终端结构传播的控制信号在对应于IC组件的相对位置的逐渐更新的时间到达各个IC组件的地址/控制输入。

公开(公告)号：US09304579B2

公开(公告)日：2016-04-05

申请号：US14798050

申请日：2015-07-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Jared L. Zerbe ,  Brian S. Leibowitz

IPC: G11C5/14 ,  G06F1/32 ,  G11C11/4072 ,  G11C11/4076 ,  G11C7/22 ,  G06F3/06 ,  G11C7/04

CPC classification number: G06F1/3275 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F2213/0038 ,  G11C5/14 ,  G11C5/148 ,  G11C7/04 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2207/2254

Abstract: A memory controller is transitioned to a low-power mode in which an active-mode resource required to transmit memory access commands to a memory device at a first command-signaling frequency is disabled. The memory controller transmits a first memory access command to the memory device using an alternative signaling resource during a transitional interval in which the active-mode resource is re-enabled.

Abstract translation: 存储器控制器转换到低功率模式，其中禁用以第一命令信令频率将存储器访问命令发送到存储器设备所需的主动模式资源。 存储器控制器在其中重新启用活动模式资源的过渡间隔期间使用替代信令资源向存储器设备发送第一存储器访问命令。

公开(公告)号：US09298543B2

公开(公告)日：2016-03-29

申请号：US14806011

申请日：2015-07-22

Applicant: Rambus Inc.

Inventor： Yuanlong Wang ,  Frederick A. Ware

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09 ,  H03M13/29 ,  G06F3/06 ,  G06F13/42 ,  H04L1/08 ,  H04L1/18 ,  G06F11/14 ,  G06F11/07 ,  H04L1/00

CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.