公开(公告)号：US20170213650A1

公开(公告)日：2017-07-27

申请号：US15004282

申请日：2016-01-22

Applicant: Micron Technology, Inc.

Inventor： Fred D. Fishburn

IPC: H01G4/38 ,  H01G4/30

CPC classification number: H01G4/385 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H01G4/40 ,  H01L23/642 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H01L28/00 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16265 ,  H01L2924/19041 ,  H01L2924/19104 ,  H05K1/162 ,  H05K2201/09763 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

公开(公告)号：US20150070238A1

公开(公告)日：2015-03-12

申请号：US14268082

申请日：2014-05-02

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: H01Q9/04

CPC classification number: H01Q9/0414 ,  B82Y30/00 ,  C04B2235/768 ,  C04B2235/781 ,  H01C7/003 ,  H01C17/003 ,  H01C17/06533 ,  H01G4/10 ,  H01G4/1209 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/642 ,  H01L23/647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01025 ,  H01L2924/01037 ,  H01L2924/01057 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01Q1/2283 ,  H01Q1/38 ,  H01Q15/0086 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/207 ,  H05K2201/017 ,  H05K2201/0175 ,  H05K2201/09763 ,  H05K2203/016 ,  H05K2203/0338 ,  H05K2203/121 ,  Y10T428/12493

Abstract: An electrical component provides a ceramic element located on or in a dielectric substrate between and in contact with a pair of electrical conductors, wherein the ceramic element includes one or more metal oxides having fluctuations in metal-oxide compositional uniformity less than or equal to 1.5 mol % throughout the ceramic element. A method of fabricating an electrical component, provides or forming a ceramic element between and in contact with a pair of electrical conductors on a substrate including depositing a mixture of metalorganic precursors and causing simultaneous decomposition of the metal oxide precursors to form the ceramic element including one or more metal oxides.

Abstract translation: 电气部件提供位于电介质基板上或介质基板之间的陶瓷元件，其与一对电导体接触并接触，其中陶瓷元件包括一种或多种具有小于或等于1.5摩尔的金属 - 氧化物组成均匀性波动的金属氧化物 ％整个陶瓷元件。 一种制造电气部件的方法，在衬底上提供或形成与一对电导体接触的陶瓷元件，包括沉积金属有机前体的混合物并引起金属氧化物前体的同时分解以形成陶瓷元件，包括一个 或更多的金属氧化物。

公开(公告)号：US08642898B2

公开(公告)日：2014-02-04

申请号：US13565075

申请日：2012-08-02

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

公开(公告)号：US08585937B2

公开(公告)日：2013-11-19

申请号：US13359105

申请日：2012-01-26

Applicant: Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

Inventor： Nathan P. Lower ,  Ross K. Wilcoxon ,  Alan P. Boone ,  Nathaniel P. Wyckoff ,  Brandon C. Hamilton

IPC: H01B1/02 ,  H01B1/06

CPC classification number: H05K1/162 ,  H01L2924/0103 ,  H01L2924/01057 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/167 ,  H05K2201/09763

Abstract: A method for forming an embedded passive device module comprises depositing a first amount of an alkali silicate material, co-depositing an amount of embedded passive device material with the amount of alkali silicate material; and thermally processing the amount of alkali silicate material and the amount of embedded passive device material at a temperature sufficient to cure the amount of alkali silicate material and the amount of embedded passive device material and form a substantially moisture free substrate.

Abstract translation: 一种用于形成嵌入式无源器件模块的方法，包括沉积第一量的碱金属硅酸盐材料，将一定量的嵌入的无源器件材料与一定量的碱金属硅酸盐材料共沉积; 并且在足以固化碱金属硅酸盐材料的量和嵌入的无源器件材料的量并形成基本上无水的衬底的温度下热处理碱金属硅酸盐材料的量和嵌入的无源器件材料的量。

公开(公告)号：US08410536B2

公开(公告)日：2013-04-02

申请号：US13345227

申请日：2012-01-06

Applicant: John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

Inventor： John D. Prymak ,  Chris Stolarski ,  Alethia Melody ,  Antony P. Chacko ,  Gregory J. Dunn

IPC: H01L27/108 ,  H01G4/005

CPC classification number: H05K1/162 ,  H01G9/012 ,  H01G9/042 ,  H01G9/045 ,  H01G9/15 ,  H05K3/429 ,  H05K2201/0329 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/09909 ,  H05K2203/0315 ,  Y10T29/417 ,  Y10T29/435

Abstract: A process for forming a laminate with capacitance and the laminate formed thereby. The process includes the steps of providing a substrate and laminating a conductive foil on the substrate wherein the foil has a dielectric. A conductive layer is formed on the dielectric. The conductive foil is treated to electrically isolate a region of conductive foil containing the conductive layer from additional conductive foil. A cathodic conductive couple is made between the conductive layer and a cathode trace and an anodic conductive couple is made between the conductive foil and an anode trace.

Abstract translation: 一种用于形成具有电容的叠层的方法和由此形成的层压体。 该方法包括以下步骤：提供衬底并将导电箔层压在衬底上，其中箔具有电介质。 在电介质上形成导电层。 处理导电箔以将包含导电层的导电箔的区域与另外的导电箔电隔离。 在导电层和阴极迹线之间形成阴极导电对，并且在导电箔和阳极迹线之间形成阳极导电耦合。

公开(公告)号：US08391017B2

公开(公告)日：2013-03-05

申请号：US12763433

申请日：2010-04-20

Applicant: David Ross McGregor ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

Inventor： David Ross McGregor ,  Cheong-Wo Hunter Chan ,  Lynne E. Dellis ,  Fuhan Liu ,  Deepukumar M. Nair ,  Venkatesh Sundaram

IPC: H01L29/86 ,  H01L21/768 ,  H01L21/50 ,  H01L23/522

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/4652 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/10674 ,  H05K2203/1126

Abstract: Provided are semiconductor packages comprising at least one thin-film capacitor attached to a printed wiring board core through build-up layers, wherein a first electrode of the thin-film capacitor comprises a thin nickel foil, a second electrode of the thin-film capacitor comprises a copper electrode, and a copper layer is formed on the nickel foil. The interconnections between the thin-film capacitor and the semiconductor device provide a low inductance path to transfer charge to and from the semiconductor device. Also provided are methods for fabricating such semiconductor packages.

Abstract translation: 提供了包括通过堆积层附着到印刷线路板芯的至少一个薄膜电容器的半导体封装，其中薄膜电容器的第一电极包括薄镍箔，薄膜电容器的第二电极 包括铜电极，并且在镍箔上形成铜层。 薄膜电容器和半导体器件之间的互连提供了将电荷转移到半导体器件和从半导体器件传输电荷的低电感路径。 还提供了制造这种半导体封装的方法。

公开(公告)号：US08357753B2

公开(公告)日：2013-01-22

申请号：US12141137

申请日：2008-06-18

Applicant: John D. Summers ,  Thomas Eugene Dueber

Inventor： John D. Summers ,  Thomas Eugene Dueber

IPC: C08G69/32 ,  C08G69/26 ,  C08G69/46 ,  H01G4/224

CPC classification number: H05K1/162 ,  C08G69/00 ,  C08G73/22 ,  H01L51/5253 ,  H05K3/1291 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这些组合物用于保护涂层，特别是电子器件的用途。 本发明涉及涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。

公开(公告)号：US20120292089A1

公开(公告)日：2012-11-22

申请号：US13565075

申请日：2012-08-02

Applicant: Chung-Cheng LIEN ,  Chih-Kui Yang

Inventor： Chung-Cheng LIEN ,  Chih-Kui Yang

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

公开(公告)号：US08233261B2

公开(公告)日：2012-07-31

申请号：US12514822

申请日：2007-12-11

Applicant: John D Summers ,  Tsutomu Mutoh

Inventor： John D Summers ,  Tsutomu Mutoh

IPC: H01G4/00 ,  H01G4/06

CPC classification number: H05K1/162 ,  H01G4/224 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/1291 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/0187 ,  H05K2201/0355 ,  H05K2201/09763 ,  H05K2203/1126 ,  H01L2924/00

Abstract: This invention relates to compositions, and the use of such compositions for protective coatings, particularly of electronic devices. The invention concerns a fired-on-foil ceramic capacitors coated with a composite encapsulant and embedded in a printed wiring board.

Abstract translation: 本发明涉及组合物，以及这些组合物用于保护涂层，特别是电子器件的用途。 本发明涉及一种涂覆有复合密封剂并嵌入印刷线路板的烧制箔陶瓷电容器。

公开(公告)号：US08115113B2

公开(公告)日：2012-02-14

申请号：US12216747

申请日：2008-07-10

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/162 ,  H05K1/0269 ,  H05K1/112 ,  H05K3/205 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/09718 ,  H05K2201/09763 ,  H05K2201/09918 ,  H05K2203/166

Abstract: A multilayer printed wiring board including a layered capacitor section provided on a first interlayer resin insulation layer and a high dielectric layer and first and second layered electrodes that sandwich the high dielectric layer. A second interlayer resin insulation layer is provided on the first insulation layer and the capacitor section, and a metal thin-film layer is provided over the capacitor section and on the second insulation layer. An outermost interlayer resin insulation layer is provided on the second insulation layer and the metal thin-film layer. A mounting section is provided on the outermost insulation layer and has first and second external terminals to mount a semiconductor element. Multiple via conductors penetrate each insulation layer. The via conductors include first via conductors that electrically connect the first layered electrode to the first external terminals. Second via conductors electrically connect the second layered electrode to the second external terminals.

Abstract translation: 一种多层印刷线路板，包括设置在第一层间树脂绝缘层和高电介质层上的层状电容器部分和夹着高电介质层的第一和第二层状电极。 在第一绝缘层和电容器部分上设置第二层间树脂绝缘层，并且在电容器部分和第二绝缘层上设置金属薄膜层。 在第二绝缘层和金属薄膜层上设置最外层的层间树脂绝缘层。 安装部分设置在最外层绝缘层上，并且具有安装半导体元件的第一和第二外部端子。 多个通孔导体穿过每个绝缘层。 通孔导体包括将第一层状电极电连接到第一外部端子的第一通孔导体。 第二通孔导体将第二层状电极电连接到第二外部端子。