公开(公告)号：US20110001246A1

公开(公告)日：2011-01-06

申请号：US12883031

申请日：2010-09-15

申请人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi FURUSAWA ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/48

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US07605448B2

公开(公告)日：2009-10-20

申请号：US11220603

申请日：2005-09-08

申请人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Noriko Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L21/56

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device according to the invention is a semiconductor device which includes a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls in closed loop form in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 根据本发明的半导体器件是一种半导体器件，其包括相对介电常数小于3.5的低介电常数膜，在平面图中设置有一个或多个密闭环，其为闭环形式的防潮壁 并且其中至少一个所述密封环包括在芯片角附近以向内突出形式的密封环突出部分。

公开(公告)号：US06903445B2

公开(公告)日：2005-06-07

申请号：US10896885

申请日：2004-07-23

申请人： Daisuke Ryuzaki ,  Takeshi Furusawa

发明人： Daisuke Ryuzaki ,  Takeshi Furusawa

IPC分类号： H01L23/522 ,  H01L21/312 ,  H01L21/316 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L31/0328

CPC分类号： H01L21/76826 ,  C23C16/0272 ,  C23C16/401 ,  H01L21/02126 ,  H01L21/02131 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02362 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3143 ,  H01L21/3148 ,  H01L21/31629 ,  H01L21/31633 ,  H01L21/3185 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819 ,  H01L21/76822 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/7684

摘要： Disclosed is a semiconductor device having a dielectric film of a stacked structure, comprising a low dielectric constant film containing silicon, oxygen and carbon a modified layer for the low dielectric constant film containing silicon, oxygen, carbon and fluorine and a dielectric protection film formed successively on a semiconductor substrate, the semiconductor device being manufactured by applying a plasma treatment using a fluorine-containing gas to the surface of an organic siloxane film to form a modified layer and then forming a dielectric protection film, which can improve the adhesivity with the dielectric protection film without increasing the dielectric constant of the organic siloxane film to prevent delamination.

摘要翻译： 公开了具有叠层结构的电介质膜的半导体器件，包括含有硅，氧和碳的低介电常数膜，用于含有硅，氧，碳和氟的低介电常数膜的改性层和相继形成的介电保护膜 在半导体衬底上，半导体器件是通过使用含氟气体的等离子体处理施加到有机硅氧烷膜的表面上以形成改性层，然后形成电介质保护膜来制造的，这可以改善与电介质的粘附性 保护膜不增加有机硅氧烷膜的介电常数，防止分层。

公开(公告)号：US06599830B2

公开(公告)日：2003-07-29

申请号：US10187998

申请日：2002-07-03

申请人： Takeshi Furusawa ,  Takao Kumihashi ,  Shuntaro Machida

发明人： Takeshi Furusawa ,  Takao Kumihashi ,  Shuntaro Machida

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/3122 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： To provide a method for manufacturing a semiconductor device, by which it is possible to form a trench or a hole with high aspect ratio on a methylsiloxane type film with low dielectric constant with causing neither via-connection failure nor short-circuit failure even when lower level interconnect is covered with etching stopper. The method comprises the processes of forming a layered film with a silicon oxide film on upper layer of a methylsiloxane type film and forming the layered film using a hard mask. When the etching stopper is etched, the silicon oxide film acts as a hard mask for the methylsiloxane type film, and transfer of faceting to the methylsiloxane type film is prevented. Thus, parasitic capacitance of multi-level interconnect can be reduced without causing via-connection failure and short failure.

公开(公告)号：US08772648B2

公开(公告)日：2014-07-08

申请号：US13442921

申请日：2012-04-10

申请人： Toshiki Furutani ,  Takeshi Furusawa

发明人： Toshiki Furutani ,  Takeshi Furusawa

IPC分类号： H05K1/11

CPC分类号： H05K1/113 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/107 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K3/428 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0542 ,  H05K2203/166 ,  H05K2203/167 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A method for manufacturing a printed wiring board, in which filled vias with a reduction in faulty connections are formed, and providing such a printed wiring board. After an electroless plated film is formed on an inner wall of a via opening, electrolytic plating is performed on insulative resin base material; the via opening is filled with plating metal and a filled via is formed. Therefore, during electrolytic plating, a plating metal is deposited from electroless plated film on the side wall of the via opening as well as from the bottom of the via opening. As a result, the via opening may be completely filled through electrolytic plating, forming a filled via with a reduction in faulty connections.

摘要翻译： 一种制造印刷线路板的方法，其中形成了具有减少连接故障的填充过孔，并且提供了这种印刷线路板。 在通孔开口的内壁上形成无电镀膜后，对绝缘性树脂基材进行电解电镀; 通孔开口填充有电镀金属，并形成填充的通孔。 因此，在电解电镀期间，电化学金属由通孔开口的侧壁以及通孔开口的底部的无电镀膜沉积。 结果，通孔开口可以通过电解电镀完全填充，形成填充的通孔，同时减少连接错误。

公开(公告)号：US08347493B2

公开(公告)日：2013-01-08

申请号：US12369115

申请日：2009-02-11

申请人： Hirotaka Taniguchi ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

发明人： Hirotaka Taniguchi ,  Toshiki Furutani ,  Takeshi Furusawa ,  Takashi Kariya

IPC分类号： H05K3/30 ,  H05K3/00 ,  H05K3/02 ,  H01R9/00

CPC分类号： H05K1/187 ,  H01L21/563 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3135 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K3/205 ,  H05K3/428 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/4913 ,  Y10T29/49133 ,  Y10T29/49139 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  H01L2924/00012 ,  H01L2924/00

摘要： A method of manufacturing a wiring board with a built-in electronic component including providing a first base material having a support body and a first metal foil detachably adhered on the support body, forming a connection terminal for mounting an electronic component on the first metal foil of the first base material by an additive method, mounting an electronic component to the connection terminal such that the electronic component is electrically connected to the connection terminal and mounted on the first base material, covering the electronic component with an insulative material structure having a hollow portion such that the electronic component is accommodated in the hollow portion of the insulative material structure after the mounting and detaching the support body from the first metal foil such that a substrate having the first base material and the insulative material structure is formed.

摘要翻译： 一种制造具有内置电子部件的布线板的方法，包括提供具有支撑体的第一基材和可拆卸地粘附在所述支撑体上的第一金属箔，形成用于将电子部件安装在所述第一金属箔上的连接端子 通过添加方法将电子部件安装到连接端子上，使得电子部件电连接到连接端子并安装在第一基材上，用绝缘材料结构覆盖电子部件，该绝缘材料结构具有中空部分 使得在将支撑体从第一金属箔安装和拆卸之后，电子部件容纳在绝缘材料结构的中空部分中，从而形成具有第一基材和绝缘材料结构的基板。

公开(公告)号：US20110215447A1

公开(公告)日：2011-09-08

申请号：US13112738

申请日：2011-05-20

申请人： Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

发明人： Takeshi Furusawa ,  Norio Miura ,  Kinya Goto ,  Masazumi Matsuura

IPC分类号： H01L23/58

CPC分类号： H01L23/585 ,  H01L23/3192 ,  H01L23/53295 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a low dielectric constant film of which the relative dielectric constant is less than 3.5, is provided with one or more seal rings that are moisture blocking walls forming a closed loop in a plan view, and where at least one of the seal rings includes a seal ring protrusion portion in inward protruding form in the vicinity of a chip corner.

摘要翻译： 包括相对介电常数小于3.5的低介电常数膜的半导体器件设置有一个或多个密封环，该密封环是在平面图中形成闭环的防潮壁，并且其中至少一个密封件 环在芯片角附近包括向内突出形式的密封环突出部。

公开(公告)号：US07700487B2

公开(公告)日：2010-04-20

申请号：US11622767

申请日：2007-01-12

申请人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

发明人： Takeshi Furusawa ,  Daisuke Kodama ,  Masahiro Matsumoto ,  Hiroshi Miyazaki

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。

公开(公告)号：US20080230847A1

公开(公告)日：2008-09-25

申请号：US12014078

申请日：2008-01-14

申请人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

发明人： Takeshi Furusawa ,  Takao Kamoshima ,  Masatsugu Amishiro ,  Naohito Suzumura ,  Shoichi Fukui ,  Masakazu Okada

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76883

摘要： The reliability of a semiconductor device having an embedded wire in the lowest layer wire is improved. In a main surface of a semiconductor substrate, MISFETs are formed and over the main surface, insulating films 10, 11 are formed. In the insulating films 10, 11 a contact hole is formed and a plug is embedded therein. Over the insulating film 11 in which the plug is embedded, insulating films 14, 15, 16 are formed and an opening is formed in the insulating films 14, 15, 16 and a wire is embedded therein. The insulating film 15 is an etching stopper film when etching the insulating film 16 in order to form the opening, containing silicon and carbon. The insulating film 11 has a high hygroscopicity and the insulating film 15 has a low moisture resistance, however, by interposing the insulating film 14 therebetween and making the insulating film 14 have a higher density of the number of Si (silicon) atoms than that of the insulating film 11, an electrically weak interface is prevented from being formed.

摘要翻译： 提高了在最低层布线中具有嵌入线的半导体器件的可靠性。 在半导体衬底的主表面中，形成MISFET，并且在主表面上形成绝缘膜10,11。 在绝缘膜10,11中形成有接触孔，并且插入插头。 在插入插头的绝缘膜11上形成绝缘膜14,15,16，并且在绝缘膜14,15,16中形成开口，并且在其中嵌入线。 绝缘膜15是在蚀刻绝缘膜16以形成包含硅和碳的开口时的蚀刻停止膜。 绝缘膜11具有高的吸湿性，绝缘膜15具有低的耐湿性，然而，通过在其间插入绝缘膜14，使得绝缘膜14具有比Si（硅）原子数更高的Si（硅）原子数 绝缘膜11，电阻弱的界面被防止形成。

公开(公告)号：US20070167010A1

公开(公告)日：2007-07-19

申请号：US11622767

申请日：2007-01-12

申请人： Takeshi FURUSAWA ,  Daisuke KODAMA ,  Masahiro MATSUMOTO ,  Hiroshi MIYAZAKI

发明人： Takeshi FURUSAWA ,  Daisuke KODAMA ,  Masahiro MATSUMOTO ,  Hiroshi MIYAZAKI

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

摘要翻译： 为了提供一种半导体器件，其具有在铜合金布线和通孔之间的连接面上形成含有氮的阻挡金属膜的结构，其中可以防止铜合金布线和通孔之间的电阻上升， 并且可以防止电阻变化。 根据本发明的半导体器件包括第一铜合金布线，通孔和第一阻挡金属膜。 第一铜合金布线形成在层间绝缘膜中，并且在主要成分Cu中含有预定的添加元素。 通孔形成在层间绝缘膜中并与第一铜合金布线的上表面电连接。 第一阻挡金属膜形成为与第一铜合金布线和通孔之间的连接部分中的第一铜合金布线接触并且包含氮。 预定的添加元素与氮反应形成高电阻部分。 此外，预定添加元素的浓度不大于0.04重量％。