公开(公告)号：US10096512B2

公开(公告)日：2018-10-09

申请号：US15290005

申请日：2016-10-11

Applicant: Applied Materials, Inc.

Inventor： Erica Chen ,  Ludovic Godet ,  Srinivas D. Nemani ,  Ellie Y. Yieh

IPC: H01L21/768 ,  H01L21/3115 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L21/3105 ,  H01L21/321

Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.

公开(公告)号：US10048589B2

公开(公告)日：2018-08-14

申请号：US15793935

申请日：2017-10-25

Applicant: Applied Materials, Inc.

Inventor： Ludovic Godet ,  Sang Ki Nam ,  Christine Y. Ouyang

IPC: G03F7/36 ,  G03F7/38

Abstract: Embodiments described herein generally relate to methods for mitigating patterning defects. More specifically, embodiments described herein relate to utilizing field guided post exposure bake processes to mitigate microbridge photoresist defects. An electric field may be applied to a substrate being processed during a post exposure bake process. Photoacid generated as a result of the exposure may be moved along a direction defined by the electric field. The movement of the photoacid may contact microbridge defects and facilitate the removal of the microbridge defects from the surface of a substrate.

公开(公告)号：US09829790B2

公开(公告)日：2017-11-28

申请号：US14733923

申请日：2015-06-08

Applicant: Applied Materials, Inc.

Inventor： Douglas A. Buchberger, Jr. ,  Sang Ki Nam ,  Viachslav Babayan ,  Christine Y. Ouyang ,  Ludovic Godet ,  Srinivas D. Nemani

IPC: G03F7/20 ,  G03F7/004 ,  G03F7/38

CPC classification number: G03F7/0045 ,  G03F7/38 ,  G03F7/70 ,  G03F7/70866

Abstract: Methods disclosed herein provide apparatus and method for applying an electric field and/or a magnetic field to a photoresist layer without air gap intervention during photolithography processes. In one embodiment, an apparatus includes a processing chamber comprising a substrate support having a substrate supporting surface, a heat source embedded in the substrate support configured to heat a substrate positioned on the substrate supporting surface, an electrode assembly configured to generate an electric field in a direction substantially perpendicular to the substrate supporting surface, wherein the electrode assembly is positioned opposite the substrate supporting surface having a downward surface facing the substrate supporting surface, wherein the electrode assembly is spaced apart from substrate support defining a processing volume between the electrode assembly and the substrate supporting surface, and a confinement ring disposed on an edge of the substrate support or the electrode assembly configured to retain an intermediate medium.

公开(公告)号：US09823570B2

公开(公告)日：2017-11-21

申请号：US14677552

申请日：2015-04-02

Applicant: Applied Materials, Inc.

Inventor： Ludovic Godet ,  Sang Ki Nam ,  Christine Y Ouyang

IPC: G03F7/36 ,  G03F7/38

CPC classification number: G03F7/38

Abstract: Embodiments described herein generally relate to methods for mitigating patterning defects. More specifically, embodiments described herein relate to utilizing field guided post exposure bake processes to mitigate microbridge photoresist defects. An electric field may be applied to a substrate being processed during a post exposure bake process. Photoacid generated as a result of the exposure may be moved along a direction defined by the electric field. The movement of the photoacid may contact microbridge defects and facilitate the removal of the microbridge defects from the surface of a substrate.

公开(公告)号：US09528185B2

公开(公告)日：2016-12-27

申请号：US14489398

申请日：2014-09-17

Applicant: Applied Materials, Inc.

Inventor： Sang Ki Nam ,  Tae Seung Cho ,  Ludovic Godet ,  Srinivas D. Nemani

IPC: H01L21/00 ,  C23C16/00 ,  C23C16/455 ,  H01J37/32 ,  C23C16/509 ,  C23C16/52

CPC classification number: C23C16/45565 ,  C23C16/5096 ,  C23C16/52 ,  H01J37/32082 ,  H01J37/32357 ,  H01J37/3244

Abstract: The present invention provides an apparatus having a plasma profile control plate disposed in a plasma processing chamber so as to locally alter plasma density to provide uniform plasma distribution across a substrate surface during processing. In one embodiment, a process kit includes a plate configured to be disposed in a plasma processing chamber, a plurality of apertures formed therethrough, the apertures configured to permit processing gases to flow through the plate, and an array of unit cells including at least one aperture formed in the plate, wherein each unit cell has an electrode assembly individually controllable relative to electrode assemblies disposed in at least two other unit cells.

Abstract translation: 本发明提供了一种装置，其具有设置在等离子体处理室中的等离子体轮廓控制板，从而局部地改变等离子体密度，以在处理期间在衬底表面上提供均匀的等离子体分布。 在一个实施例中，处理套件包括被配置为设置在等离子体处理室中的板，通过其形成的多个孔，所述孔被构造成允许处理气体流过板，以及包括至少一个 孔，其中每个单元电池具有相对于设置在至少两个其它单元电池中的电极组件可独立控制的电极组件。

公开(公告)号：US09515166B2

公开(公告)日：2016-12-06

申请号：US14276780

申请日：2014-05-13

Applicant: Applied Materials, Inc.

Inventor： Srinivas D. Nemani ,  Ellie Y. Yieh ,  Ludovic Godet ,  Yin Fan

IPC: H01L21/469 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3115 ,  H01J37/32

CPC classification number: H01L21/02304 ,  H01J37/32357 ,  H01J37/32403 ,  H01J37/32422 ,  H01L21/0228 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/31155 ,  H01L29/66795 ,  H01L29/66803

Abstract: Methods for forming fin structure with desired materials formed on different locations of the fin structure using a selective deposition process for three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips are provided. In one embodiment, a method of forming a structure with desired materials on a substrate includes forming a patterned self-assembled monolayer on a circumference of a structure formed on a substrate, wherein the patterned self-assembled monolayer includes a treated layer formed among a self-assembled monolayer, and performing an atomic layer deposition process to form a material layer predominantly on the self-assembled monolayer from the patterned self-assembled monolayer.

Abstract translation: 提供了使用用于半导体芯片的鳍式场效应晶体管（FinFET）的三维（3D）堆叠的选择性沉积工艺在翅片结构的不同位置形成所需材料的翅片结构的方法。 在一个实施方案中，在衬底上形成具有期望材料的结构的方法包括在形成在衬底上的结构的圆周上形成图案化的自组装单层，其中所述图案化的自组装单层包括在自身中形成的处理层 并且执行原子层沉积工艺，以从图案化的自组装单层形成主要在自组装单层上的材料层。

公开(公告)号：US09502262B2

公开(公告)日：2016-11-22

申请号：US14833858

申请日：2015-08-24

Applicant: Applied Materials, Inc.

Inventor： Yongmei Chen ,  Christopher S. Ngai ,  Jingjing Liu ,  Jun Xue ,  Chentsau Ying ,  Ludovic Godet

IPC: C23C16/27 ,  H01L21/31 ,  H01L21/311 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L21/0332 ,  C23C16/26 ,  C23C16/27 ,  C23C16/274 ,  C23C16/279 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/49 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/518

Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.

Abstract translation: 本文公开了用于形成半导体器件的纳米晶体金刚石层及其使用方法。 该器件可以包括具有处理表面和支撑表面的衬底，形成在处理表面上的器件层和形成在处理层上的纳米晶体金刚石层，该纳米晶体金刚石层的平均晶粒尺寸在2nm和5nm之间 。 该方法可以包括将衬底定位在处理室中，在处理表面上沉积器件层，在器件层上沉积纳米晶体金刚石层，平均晶粒尺寸在2nm和5nm之间的纳米晶体金刚石层，图案化和 蚀刻纳米晶体金刚石层，蚀刻器件层以形成特征并从器件层的表面灰化纳米晶体金刚石层。

公开(公告)号：US20160181112A1

公开(公告)日：2016-06-23

申请号：US14581332

申请日：2014-12-23

Applicant: Applied Materials, Inc.

Inventor： Jun Xue ,  Ching-Mei Hsu ,  Zihui Li ,  Ludovic Godet ,  Anchuan Wang ,  Nitin K. Ingle

IPC: H01L21/3065 ,  H01L21/265

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32366 ,  H01J37/32422 ,  H01J37/3244 ,  H01J37/32954 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/3223

Abstract: A method of anisotropically dry-etching exposed substrate material on a patterned substrate is described. The patterned substrate has a gap formed in a single material made from, for example, a silicon-containing material or a metal-containing material. The method includes directionally ion-implanting the patterned structure to implant the bottom of the gap without implanting substantially the walls of the gap. Subsequently, a remote plasma is formed using a fluorine-containing precursor to etch the patterned substrate such that either (1) the walls are selectively etched relative to the floor of the gap, or (2) the floor is selectively etched relative to the walls of the gap. Without ion implantation, the etch operation would be isotropic owing to the remote nature of the plasma excitation during the etch process.

Abstract translation: 描述了在图案化衬底上各向异性地干蚀刻暴露的衬底材料的方法。 图案化衬底具有由例如含硅材料或含金属材料制成的单一材料形成的间隙。 该方法包括定向离子注入图案化结构以植入间隙的底部，而基本上不插入间隙的壁。 随后，使用含氟前体形成远程等离子体以蚀刻图案化衬底，使得（1）相对于间隙的底板选择性地蚀刻壁，或者（2）相对于壁选择性地蚀刻地板 的差距。 在没有离子注入的情况下，蚀刻操作将是各向同性的，这是由于在蚀刻过程期间等离子体激发的远程特性。

公开(公告)号：US09366966B2

公开(公告)日：2016-06-14

申请号：US14478403

申请日：2014-09-05

Applicant: Applied Materials, Inc.

Inventor： Peng Xie ,  Ludovic Godet

IPC: G03F7/26 ,  G03F7/20

CPC classification number: G03F7/26 ,  G03F7/0045 ,  G03F7/091 ,  G03F7/094 ,  G03F7/168 ,  G03F7/2051 ,  G03F7/38

Abstract: Methods and apparatuses for minimizing line edge/width roughness in lines formed by photolithography are provided. In one example, a method of processing a substrate, the method includes applying a photoresist layer comprising a photoacid generator to a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to a radiation light in a lithographic exposure process, and applying an electric field or a magnetic field to alter movement of photoacid generated from the photoacid generator substantially in a vertical direction.

Abstract translation: 提供了通过光刻形成的线中的线边缘/宽度粗糙度最小化的方法和装置。 在一个实例中，一种处理衬底的方法，所述方法包括将包含光致酸产生剂的光致抗蚀剂层施加到衬底上，将未被光掩模保护的光致抗蚀剂层的第一部分暴露于光刻曝光工艺中的辐射光，并施加 电场或磁场，以改变基本上沿垂直方向从光致酸发生器产生的光酸的运动。

公开(公告)号：US20160079034A1

公开(公告)日：2016-03-17

申请号：US14485505

申请日：2014-09-12

Applicant: Applied Materials Inc.

Inventor： Ellie Y. Yieh ,  Ludovic Godet ,  Jun Xue ,  Srinivas D. Nemani ,  DongQing (Karen) Li ,  Erica Chen

IPC: H01J37/317

CPC classification number: H01L21/26506 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02321 ,  H01L21/02323 ,  H01L21/0337 ,  H01L21/3065 ,  H01L21/31155 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795

Abstract: Species are supplied to a flowable layer over a substrate. A property of the flowable layer is modified by implanting the species to the flowable layer. The property comprises a density, a stress, a film shrinkage, an etch selectivity, or any combination thereof.

Abstract translation: 物质被提供到基底上的可流动层。 可流动层的性质通过将物种注入可流动层来改变。 该性质包括密度，应力，薄膜收缩率，蚀刻选择性或其任何组合。