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    Method for multiple spacer width control
    21.
    发明授权
    Method for multiple spacer width control 有权
    多间隔宽度控制方法

    公开(公告)号：US07176137B2

    公开(公告)日：2007-02-13

    申请号：US10435009

    申请日：2003-05-09

    Applicant: Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    Inventor： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    IPC: H01L21/302

    CPC classification number: H01L29/6656 ,  H01L21/823468

    Abstract: A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

    Abstract translation: 形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

    Low temperature method to form low k dielectric
    23.
    发明授权
    Low temperature method to form low k dielectric 有权
    低温方法形成低k电介质

    公开(公告)号：US06197706B1

    公开(公告)日：2001-03-06

    申请号：US09607042

    申请日：2000-06-30

    Applicant: Lain-Jang Li ,  Cheng-Chung Lin ,  Syun-Ming Jang

    Inventor： Lain-Jang Li ,  Cheng-Chung Lin ,  Syun-Ming Jang

    IPC: H01L2131

    CPC classification number: H01L21/3146

    Abstract: Black diamond films, deposited using PECVD at low substrate temperatures, have been effectively stabilized by immersing them in de-ionized water at a temperature of about 90° C. for about 20 minutes or in a hydrogen peroxide solution (typically at a concentration of 10%) for about 60 minutes. Since it has been observed that the dielectric constant of the stabilized film increases with both immersion time and/or peroxide concentration, this effect may be used as a means for adjusting the dielectric constant of a black diamond film. Standard analytical techniques confirm that these low temperature stabilized films have electrical properties that are at least as good as those of films stabilized using high temperature heat treatments.

    Abstract translation: 通过在约90℃的温度下将它们浸入去离子水中约20分钟或在过氧化氢溶液中（通常浓度为10），已经有效地稳定了在低基材温度下使用PECVD沉积的黑色金刚石膜 ％）约60分钟。 由于已经观察到稳定的膜的介电常数随着浸渍时间和/或过氧化物浓度的增加而增加，所以该效果可以用作调整黑色金刚石膜的介电常数的手段。 标准分析技术证实这些低温稳定膜的电性能至少与使用高温热处理稳定的膜的电性能一样好。

    Conditional cell placement
    24.
    发明授权
    Conditional cell placement 有权
    条件细胞放置

    公开(公告)号：US08560997B1

    公开(公告)日：2013-10-15

    申请号：US13557578

    申请日：2012-07-25

    Applicant: Ping-Lin Yang ,  Ming-Zhang Kuo ,  Cheng-Chung Lin ,  Jimmy Hsiao ,  Jia-Rong Hsu

    Inventor： Ping-Lin Yang ,  Ming-Zhang Kuo ,  Cheng-Chung Lin ,  Jimmy Hsiao ,  Jia-Rong Hsu

    IPC: G06F17/50

    CPC classification number: G06F17/5072

    Abstract: Among other things, one or more techniques for conditional cell placement are provided herein. In an embodiment, a conditional boundary is created for a first cell. For example, the conditional boundary enables the first cell to be placed relative to a second cell based on a conditional placement rule. In an embodiment, the first cell is placed in a first manner relative to the second cell based in a first scenario. In a second scenario, different than the first scenario, the first cell is placed in a second manner relative to the second cell. In this manner, conditional cell placement is provided, thus providing flexibility and improved layout efficiency with regard to semiconductor fabrication, for example.

    Abstract translation: 其中还提供了一种或多种用于条件单元放置的技术。 在一个实施例中，为第一小区创建条件边界。 例如，条件边界使得能够基于条件放置规则相对于第二单元放置第一单元。 在一个实施例中，基于第一情况，第一小区相对于第二小区以第一方式放置。 在第二种情况下，与第一种情况不同，第一单元相对于第二单元以第二种方式放置。 以这种方式，提供条件单元布置，从而提供例如关于半导体制造的灵活性和改进的布局效率。

    Surface treatment of metal interconnect lines
    27.
    发明申请
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US20060001160A1

    公开(公告)日：2006-01-05

    申请号：US11213238

    申请日：2005-08-26

    Applicant: Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    Inventor： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Ta Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  B32B15/00 ,  B32B17/06

    CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    Abstract: Apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    Abstract translation: 用于形成半导体结构的装置，其包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

    Surface treatment of metal interconnect lines
    28.
    发明授权
    Surface treatment of metal interconnect lines 有权
    金属互连线的表面处理

    公开(公告)号：US06955984B2

    公开(公告)日：2005-10-18

    申请号：US10439358

    申请日：2003-05-16

    Applicant: Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Dai Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    Inventor： Wen-Kai Wan ,  Yih-Hsiung Lin ,  Ming-Dai Lei ,  Baw-Ching Perng ,  Cheng-Chung Lin ,  Chia-Hui Lin ,  Ai-Sen Liu

    IPC: H01L21/288 ,  H01L21/44 ,  H01L21/445 ,  H01L21/768

    CPC classification number: H01L21/76843 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76886

    Abstract: Methods and apparatus for forming a semiconductor structure comprising a first layer on top of a substrate wherein the first layer defines conductive regions such as copper interconnect lines and non-conductive regions such as dielectric materials. The conductive regions are covered by a second layer of a material different than the first layer such as for example nickel and then the structure is heat treated such that the interconnect lines and second metal, such as a copper interconnect line and a nickel second layer, interact with each other to form an alloy layer. The alloy layer has superior qualities for adhering to both the copper interconnect lines and a subsequently deposited dielectric material.

    Abstract translation: 用于形成半导体结构的方法和装置包括在衬底的顶部上的第一层，其中第一层限定诸如铜互连线和非导电区域（例如介电材料）的导电区域。 导电区域被不同于第一层的材料的第二层（例如镍）覆盖，然后对该结构进行热处理，使得互连线和第二金属（例如铜互连线和镍第二层） 相互作用形成合金层。 合金层具有优异的粘附于铜互连线和随后沉积的电介质材料的品质。

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