公开(公告)号：US20110068457A1

公开(公告)日：2011-03-24

申请号：US12586339

申请日：2009-09-21

申请人： Xiaotian Zhang ,  Jun Lu ,  Kai Liu

发明人： Xiaotian Zhang ,  Jun Lu ,  Kai Liu

IPC分类号： H01L23/498 ,  H01L21/56

CPC分类号： H01L24/41 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/27 ,  H01L24/29 ,  H01L24/37 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/48639 ,  H01L2224/48699 ,  H01L2224/48739 ,  H01L2224/48799 ,  H01L2224/48839 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/83856 ,  H01L2224/85399 ,  H01L2224/85439 ,  H01L2224/8585 ,  H01L2224/92 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45147 ,  H01L2924/01049 ,  H01L2924/206

摘要： This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

公开(公告)号：US20070145609A1

公开(公告)日：2007-06-28

申请号：US11316614

申请日：2005-12-22

申请人： Xiaotian Zhang ,  Argo Chang ,  James Lee ,  Ryan Huang ,  Kai Liu

发明人： Xiaotian Zhang ,  Argo Chang ,  James Lee ,  Ryan Huang ,  Kai Liu

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A composite semiconductor package is disclosed. The package includes a lead frame having first and second die bonding pads, the first and second die bonding pads having a large lateral separation therebetween, a first device bonded to the first die bonding pad, a second device bonded to the second die bonding pad, a plurality of first leads coupled to the first die bonding pad, a plurality of second leads coupled to the second die bonding pad, and an encapsulant covering the lead frame, the first and second devices and at least a portion of the first and second pluralities of leads. The package may be a TSSOP-8 composite package having a common drain MOSFET pair and an IC.

摘要翻译： 公开了一种复合半导体封装。 封装包括具有第一和第二裸片接合焊盘的引线框架，第一和第二管芯接合焊盘之间具有大的横向间隔，接合到第一管芯接合焊盘的第一器件，与第二管芯接合焊盘接合的第二器件， 耦合到第一裸片焊接焊盘的多个第一引线，耦合到第二管芯焊盘的多个第二引线以及覆盖引线框架的密封剂，第一和第二器件以及第一和第二多个元件的至少一部分 的领导。 该封装可以是具有公共漏极MOSFET对和IC的TSSOP-8复合封装。

公开(公告)号：US20060145318A1

公开(公告)日：2006-07-06

申请号：US11150489

申请日：2005-06-10

申请人： Xiaotian Zhang ,  Kai Liu ,  Mlng Sun

发明人： Xiaotian Zhang ,  Kai Liu ,  Mlng Sun

IPC分类号： H01L23/495

CPC分类号： H01L23/49562 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/73265 ,  H01L2224/85 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A DFN semiconductor package is disclosed. The package includes a leadframe having a die bonding pad formed integrally with a drain lead, a source lead bonding area and a gate lead bonding area, the source lead bonding area and the gate lead bonding area being of increased area, a die coupled to the die bonding pad, a die source bonding area coupled to the source lead bonding area and a die gate bonding area coupled to the gate lead bonding area, and an encapsulant at least partially covering the die, drain lead, gate lead bonding area and source lead bonding area.

公开(公告)号：US20160126214A1

公开(公告)日：2016-05-05

申请号：US14526518

申请日：2014-10-29

申请人： Xiaotian Zhang ,  Jun Lu ,  Kai Liu

发明人： Xiaotian Zhang ,  Jun Lu ,  Kai Liu

IPC分类号： H01L23/00

CPC分类号： H01L24/83 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49541 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/84 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/2732 ,  H01L2224/27848 ,  H01L2224/29012 ,  H01L2224/29013 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/32013 ,  H01L2224/32014 ,  H01L2224/32055 ,  H01L2224/32245 ,  H01L2224/40499 ,  H01L2224/45144 ,  H01L2224/48106 ,  H01L2224/48108 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2224/73263 ,  H01L2224/73265 ,  H01L2224/83048 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83856 ,  H01L2224/83862 ,  H01L2224/84203 ,  H01L2224/84862 ,  H01L2224/92246 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/3512 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/0781 ,  H01L2924/06 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： This invention discloses a semiconductor package with adhesive material pre-printed on the lead frame and chip, and the manufacturing method. The adhesive material is applied onto the chip carrier and the pin of the lead frame and also on the front electrode of the semiconductor chip via pre-printing. The back of the semiconductor chip is adhered on the chip carrier, and the front electrode of the semiconductor chip and the pin are connected respectively with a metal connector. The size, shape and thickness of the adhesive material are applied according to different application requirements according to size and shapes of the contact zone of the semiconductor chip and the metal connector. Particularly, the adhesive zones are formed by pre-printing the adhesive material thus significantly enhance the quality and performance of semiconductor products, and improves the productivity.

摘要翻译： 本发明公开了一种半导体封装，其具有预先印刷在引线框架和芯片上的粘合剂材料及其制造方法。 粘合剂材料通过预打印被施加到芯片载体和引线框架的引脚以及半导体芯片的前电极上。 半导体芯片的背面粘附在芯片载体上，并且半导体芯片的前电极和引脚分别与金属连接器连接。 根据不同的应用要求，根据半导体芯片和金属连接器的接触区域的尺寸和形状来施加粘合材料的尺寸，形状和厚度。 特别地，通过预先印刷粘合剂材料形成粘合剂区域，从而显着提高半导体产品的质量和性能，并提高生产率。

公开(公告)号：US20150076676A1

公开(公告)日：2015-03-19

申请号：US14029555

申请日：2013-09-17

申请人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

发明人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

IPC分类号： H01L23/495 ,  H01L25/07

CPC分类号： H01L23/492 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/97 ,  H01L2924/13091 ,  H01L2924/15156 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00

摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.

摘要翻译： 功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。 在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

公开(公告)号：US08563360B2

公开(公告)日：2013-10-22

申请号：US12479995

申请日：2009-06-08

申请人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

发明人： Jun Lu ,  François Hébert ,  Kai Liu ,  Xiaotian Zhang

IPC分类号： H01L21/00

CPC分类号： H01L23/492 ,  H01L23/04 ,  H01L24/37 ,  H01L24/40 ,  H01L25/072 ,  H01L29/0657 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40139 ,  H01L2224/73253 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/37099

摘要： A power semiconductor device package includes a conductive assembly including a connecting structure and a semiconductor die having an aperture formed therethrough, the aperture being sized and configured to spacedly receive the connecting structure. In an alternative embodiment, a power semiconductor device package includes a conductive assembly including a connecting structure and a pair of semiconductor die disposed on either side of the connecting structure in spaced relationship thereto.

摘要翻译： 功率半导体器件封装包括导电组件，其包括连接结构和具有穿过其形成的孔的半导体管芯，所述孔的尺寸和构造为间隔地接收连接结构。 在替代实施例中，功率半导体器件封装包括导电组件，该导电组件包括连接结构和设置在与之间隔开的连接结构的任一侧上的一对半导体管芯。

公开(公告)号：US20100133674A1

公开(公告)日：2010-06-03

申请号：US12330381

申请日：2008-12-08

申请人： Francois Hebert ,  Kai Liu

发明人： Francois Hebert ,  Kai Liu

IPC分类号： H01L23/538 ,  H01L21/62

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099 ,  H01L2224/84

摘要： A top-side cooled compact semiconductor package with integrated bypass capacitor is disclosed. The top-side cooled compact semiconductor package includes a circuit substrate with terminal leads, numerous semiconductor dies bonded atop the circuit substrate, numerous elevation-adaptive interconnection plates for bonding and interconnecting top contact areas of the semiconductor dies with the circuit substrate, a first member of the elevation-adaptive interconnection plates has a first flat-top area and a second member of the elevation-adaptive interconnection plates has a second flat-top area in level with the first flat-top area, a bypass capacitor, having two capacitor terminals located at its ends, stacked atop the two interconnection plate members while being bonded thereto via the first flat-top area and the second flat-top area for a reduced interconnection parasitic impedance.

摘要翻译： 公开了具有集成旁路电容器的顶侧冷却紧凑型半导体封装。 顶侧冷却的紧凑型半导体封装包括具有端子引线的电路基板，接合在电路基板顶上的多个半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的许多仰角自适应互连板，第一构件 所述高度自适应互连板具有第一平顶区域，并且所述仰角自适应互连板的第二构件具有与所述第一平顶区域平齐的第二平顶区域，具有两个电容器端子的旁路电容器 位于其端部，并且通过第一平顶部区域和第二平顶部区域结合到两个互连板构件的顶部，以减少互连寄生阻抗。

公开(公告)号：US20100133670A1

公开(公告)日：2010-06-03

申请号：US12326065

申请日：2008-12-01

申请人： Kai Liu ,  Francois Hebert ,  Lei Shi

发明人： Kai Liu ,  Francois Hebert ,  Lei Shi

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L21/56 ,  H01L21/50 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

摘要： A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

摘要翻译： 公开了一种具有堆叠互连板的顶侧冷却半导体封装。 半导体封装包括具有端子引线的电路基板，电路基板顶部的半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的低热电阻紧密互连板，低热阻堆叠互连板 位于用于顶侧冷却的紧密互连板顶部，用于封装包装的模制密封剂，除了暴露堆叠的互连板的顶表面以保持有效的顶侧冷却。 堆叠的互连板的顶部可以包括在紧密互连板上方的周边突出部。 外围悬垂允许最大化的暴露的顶部表面积用于散热，而不管适用于紧密互连板的其它面积约束。 层叠的互连板可以被部分蚀刻或三维地形成以产生外围悬垂。

公开(公告)号：US07884469B2

公开(公告)日：2011-02-08

申请号：US12474107

申请日：2009-05-28

申请人： Lei Shi ,  Ming Sun ,  Kai Liu

发明人： Lei Shi ,  Ming Sun ,  Kai Liu

IPC分类号： H01L23/34

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metallized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metallized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

摘要翻译： 公开了半导体封装。 封装包括具有漏极，源极和栅极引线的引线框架，以及耦合到引线框架的半导体管芯，半导体管芯具有多个金属化源极触点。 桥接源极板互连具有桥接部分，设置在桥接部分的任一侧上的谷部分，设置在谷部分和桥接部分两侧的平面部分以及从平面部分之一悬挂的连接部分， 将源极引线与多个金属化源触点连接的源极板互连。 桥面部分设置在平坦部分的平面上方的平面中，而平面部分设置在桥接部分的平面和谷部的平面之间的平面中。

公开(公告)号：US07622796B2

公开(公告)日：2009-11-24

申请号：US11906136

申请日：2007-09-28

申请人： Lei Shi ,  Ming Sun ,  Kai Liu

发明人： Lei Shi ,  Ming Sun ,  Kai Liu

IPC分类号： H01L23/02

CPC分类号： H01L23/49524 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73219 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is disclosed. The package includes a leadframe having drain, source and gate leads, and a semiconductor die coupled to the leadframe, the semiconductor die having a plurality of metalized source contacts. A bridged source plate interconnection has a bridge portion, valley portions disposed on either side of the bridge portion, plane portions disposed on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions, the bridged source plate interconnection connecting the source lead with the plurality of metalized source contacts. The bridge portion is disposed in a plane above the plane of the valley portions while the plane portions are disposed in a plane intermediate the plane of the bridge portion and the plane of the valley portions.

摘要翻译： 公开了半导体封装。 封装包括具有漏极，源极和栅极引线的引线框架以及耦合到引线框架的半导体管芯，该半导体管芯具有多个金属化源极触点。 桥接源极板互连具有桥接部分，设置在桥接部分的任一侧上的谷部分，设置在谷部分和桥接部分两侧的平面部分以及从平面部分之一悬挂的连接部分， 将源极引线与多个金属化源触点连接的源极板互连。 桥面部分设置在平坦部分的平面上方的平面中，而平面部分设置在桥接部分的平面和谷部的平面之间的平面中。