公开(公告)号：US20150214331A1

公开(公告)日：2015-07-30

申请号：US14168112

申请日：2014-01-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在布置在散热片上的蚀刻停止层上形成多个栅极形成层。 多个栅极形成层包括由电介质材料形成的虚拟栅极层。 图案化多个栅极形成层以在蚀刻停止层上形成多个虚拟栅极元件。 每个伪栅极元件由电介质材料形成。 蚀刻形成在虚拟栅极元件上的间隔层，以在虚拟栅极元件的每个侧壁上形成间隔物。 位于每个伪栅元件之间的蚀刻停止层的一部分被蚀刻以暴露半导体鳍片的一部分。 半导体材料从半导体鳍片的暴露部分外延生长以形成源极/漏极区域。

公开(公告)号：US10297510B1

公开(公告)日：2019-05-21

申请号：US15962536

申请日：2018-04-25

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Soon-Cheon Seo ,  Fee Li Lie ,  Linus Jang

IPC: H01L21/8238 ,  H01L29/66 ,  H01L27/092

Abstract: A method for fabricating a multiple gate width structure for an integrated circuit is described. A fin on a semiconductor substrate with a first hard mask layer is covered by a first and second sacrificial gate each of which includes a second hard mask layer. Spacer layers and a dielectric layer are formed over the first and second sacrificial gate structures. The resulting structure is planarized so that the first and second sacrificial gate structures and the dielectric layer have coplanar top surfaces. The first and second sacrificial gate structures are removed to respectively form first and second trench recesses in the dielectric layer. The trench recesses are filled with a conductor to form permanent gate structures. A first permanent gate structure is formed in the first trench recess has a first length and a second permanent gate structure is formed in the second trench recess has a second length greater than the first length.

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09842741B2

公开(公告)日：2017-12-12

申请号：US15342794

申请日：2016-11-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L21/306 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/027 ,  H01L29/78 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

公开(公告)号：US20170076954A1

公开(公告)日：2017-03-16

申请号：US15342794

申请日：2016-11-03

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L21/306 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US20160365425A1

公开(公告)日：2016-12-15

申请号：US14739662

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Samsung Electronics Co., Ltd. ,  Globalfoundries Inc.

Inventor： Hsueh-Chung Chen ,  Su Chen Fan ,  Dong Kwon Kim ,  Sean Lian ,  Fee Li Lie ,  Linus Jang

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311

CPC classification number: H01L29/6653 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/3086 ,  H01L21/31116

Abstract: An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.

Abstract translation: 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。

公开(公告)号：US09449835B2

公开(公告)日：2016-09-20

申请号：US14676097

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

公开(公告)号：US09184263B2

公开(公告)日：2015-11-10

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L21/3205 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。

公开(公告)号：US20150255299A1

公开(公告)日：2015-09-10

申请号：US14196931

申请日：2014-03-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Jin Cho ,  Ryan Ryoung-Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/3085 ,  H01L21/823431 ,  H01L21/845

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括在半导体衬底的选定区域中形成鳍结构。 该方法包括用掩模覆盖翅片结构和半导体衬底，并在掩模中形成沟槽，以在所选择的区域中限定不超过两个暴露的翅片结构。 此外，该方法包括去除暴露的翅片结构以向选定区域提供所需数量的翅片结构。

公开(公告)号：US20150187905A1

公开(公告)日：2015-07-02

申请号：US14143468

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ajey Poovannummoottil Jacob ,  Daniel T. Pham ,  Mark V. Raymond ,  Christopher M. Prindle ,  Catherine B. Labelle ,  Linus Jang ,  Robert Teagle

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/51 ,  H01L29/423 ,  H01L21/768 ,  H01L21/3105 ,  H01L29/417

CPC classification number: H01L29/6681 ,  H01L21/31055 ,  H01L21/76897 ,  H01L29/0692 ,  H01L29/4175 ,  H01L29/41791 ,  H01L29/42364 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: One method disclosed herein includes, among other things, forming sidewall spacers adjacent opposite sides of a sacrificial gate electrode of a sacrificial gate structure, forming a tensile-stressed layer of insulating material adjacent the sidewall spacers, removing the sacrificial gate structure to define a replacement gate cavity positioned between the sidewall spacers, forming a replacement gate structure in the replacement gate cavity, forming a tensile-stressed gate cap layer above the replacement gate structure and within the replacement gate cavity and, after forming the tensile-stressed gate cap layer, removing the tensile-stressed layer of insulating material.

Abstract translation: 本文公开的一种方法尤其包括邻近牺牲栅极结构的牺牲栅电极的相对侧的侧壁间隔壁，形成邻近侧壁间隔物的绝缘材料的拉应力层，去除牺牲栅极结构以限定替换 门腔定位在侧壁间隔件之间，在置换栅腔中形成替换栅极结构，在置换栅极结构之上和置换栅极腔内形成拉伸应力栅极盖层，并且在形成拉伸应力栅极盖层之后， 去除绝缘材料的拉应力层。