中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

147 records (took 0.021 seconds)

    Methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting products
    21.
    发明授权
    Methods of forming replacement gate structures on transistor devices with a shared gate structure and the resulting products 有权
    在具有共享栅极结构的晶体管器件上形成替代栅极结构的方法以及所得到的产物

    公开(公告)号：US09263446B1

    公开(公告)日：2016-02-16

    申请号：US14511286

    申请日：2014-10-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/28

    CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656

    Abstract: One illustrative method disclosed herein includes, among other things, forming a shared gate cavity that spans across an isolation region and is positioned above first and second active regions, forming at least one layer of material in the shared gate cavity above the first and second active regions and above the isolation region, forming a first masking layer that covers portions of the shared gate cavity positioned above the first and second active regions while exposing a portion of the shared gate cavity positioned above the isolation region, with the first masking layer in position, performing at least one first etching process to remove at least a portion of the at least one layer of material in the exposed portion of the shared gate cavity above the isolation region, and removing the first masking layer.

    Abstract translation: 本文公开的一种说明性方法尤其包括形成跨越隔离区并且位于第一和第二有源区上方的共享栅极腔，在第一和第二有源区上方的共享栅极腔中形成至少一层材料 区域并且在隔离区域上方，形成第一掩模层，其覆盖位于第一和第二有源区域上方的共享栅极腔的部分，同时暴露位于隔离区域上方的共享栅极腔的一部分，其中第一掩模层位于 执行至少一个第一蚀刻工艺以去除所述隔离区域上方的所述共享栅腔的所述暴露部分中的所述至少一层材料的至少一部分，以及去除所述第一掩模层。

    Methods of fabricating fin structures of uniform height
    22.
    发明授权
    Methods of fabricating fin structures of uniform height 有权
    制造均匀高度的翅片结构的方法

    公开(公告)号：US09236308B1

    公开(公告)日：2016-01-12

    申请号：US14463013

    申请日：2014-08-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Kwan-Yong Lim ,  Sukwon Hong

    IPC: H01L21/8242 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/306 ,  H01L21/311 ,  H01L29/66

    CPC classification number: H01L21/823431 ,  H01L21/30625 ,  H01L21/31051 ,  H01L21/31116 ,  H01L27/0886 ,  H01L29/66818

    Abstract: Methods of fabricating fin structures having exposed upper fin portions with a uniform exposure height are disclosed herein. The fabrication methods include providing a substrate with plurality of fins and a dielectric material disposed between and over the plurality of fins, planarizing the dielectric material and the plurality of fins, and uniformly recessing the dielectric material to a pre-selected depth below upper surfaces of the plurality of fins to expose upper fin portions. The exposed upper fin portions, as a result of uniformly recessing the dielectric material, have a uniform exposure height above the recessed dielectric material. A protective film may be provided over the recessed dielectric material and exposed upper fin portions to preserve the uniform exposure height of the upper fin portions. The uniform exposure height of the exposed upper fin portions facilitates subsequent formation of one or more circuit structures above the substrate.

    Abstract translation: 本文公开了制造具有暴露的具有均匀曝光高度的上翅片部分的翅片结构的方法。 制造方法包括提供具有多个翅片的基板和设置在多个翅片之间和之上的介电材料，平坦化介电材料和多个翅片，并均匀地将电介质材料凹陷到下表面下方的预选深度 多个翅片以暴露上部翅片部分。 暴露的上部翅片部分，由于均匀地凹陷介电材料，在凹入的电介质材料上方具有均匀的曝光高度。 可以在凹陷的电介质材料和暴露的上部翅片部分上设置保护膜，以保持上部翅片部分的均匀的曝光高度。 暴露的上部翅片部分的均匀曝光高度有助于随后在基底上方形成一个或多个电路结构。

    METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES
    24.
    发明申请
    METHODS OF FORMING EPI SEMICONDUCTOR MATERIAL IN A TRENCH FORMED ABOVE A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICES 有权
    在上述形成的半导体器件和结果器件中形成EPI半导体材料的方法

    公开(公告)号：US20150318398A1

    公开(公告)日：2015-11-05

    申请号：US14267216

    申请日：2014-05-01

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ruilong Xie ,  Hoon Kim ,  Chanro Park ,  Min Gyu Sung

    IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

    Abstract: One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, wherein a first portion of the gate structure is positioned above the active region and second portions of the gate structure are positioned above an isolation region formed in the substrate, forming a sidewall spacer adjacent opposite sides of the first portion of the gate structure so as to define first and second continuous epi formation trenches comprised of the spacer that extend for less than the axial length of the gate structure, and forming an epi semiconductor material on the active region within each of the first and second continuous epi formation trenches.

    Abstract translation: 所公开的一种方法包括在半导体衬底的有源区上方形成栅极结构，其中栅极结构的第一部分位于有源区上方，栅极结构的第二部分位于形成的隔离区的上方 在所述衬底中，形成邻近所述栅极结构的第一部分的相对侧面的侧壁间隔物，以便限定由所述间隔物组成的第一和第二连续外延形成沟槽，所述沟槽延伸小于所述栅极结构的轴向长度，并形成 在第一和第二连续外延形成沟槽的每一个内的有源区域上的外延半导体材料。

    Titanium silicide formation in a narrow source-drain contact
    25.
    发明授权
    Titanium silicide formation in a narrow source-drain contact 有权

    公开(公告)号：US10854510B2

    公开(公告)日：2020-12-01

    申请号：US15687455

    申请日：2017-08-26

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Min Gyu Sung ,  Kwanyong Lim ,  Hiroaki Niimi

    IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L29/417 ,  H01L23/485

    Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

    Air-gap spacers for field-effect transistors
    27.
    发明授权
    Air-gap spacers for field-effect transistors 有权

    公开(公告)号：US10319627B2

    公开(公告)日：2019-06-11

    申请号：US15376831

    申请日：2016-12-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

    IPC: H01L21/76 ,  H01L21/768 ,  H01L29/66

    Abstract: Structures for air-gap spacers in a field-effect transistor and methods for forming air-gap spacers in a field-effect transistor. A gate structure is formed on a top surface of a semiconductor body. A dielectric spacer is formed adjacent to a vertical sidewall of the gate structure. A semiconductor layer is formed on the top surface of the semiconductor body. The semiconductor layer is arranged relative to the vertical sidewall of the gate structure such that a first section of the first dielectric spacer is located in a space between the semiconductor layer and the vertical sidewall of the gate structure. A second section of the dielectric spacer that is located above a top surface of the semiconductor layer is removed. An air-gap spacer is formed in a space from which the second section of the dielectric spacer is removed.

Patent Agency Ranking