公开(公告)号：US20120018883A1

公开(公告)日：2012-01-26

申请号：US13248683

申请日：2011-09-29

申请人： Geng-Shin Shen ,  Jhong Bang Chyi

发明人： Geng-Shin Shen ,  Jhong Bang Chyi

IPC分类号： H01L23/498

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/12 ,  H01L2224/02125 ,  H01L2224/02145 ,  H01L2224/0215 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05019 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/11009 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13144 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/351 ,  H01L2224/13099 ,  H01L2924/0665 ,  H01L2924/07025 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2924/00

摘要： A conductive structure for a semiconductor integrated circuit is provided. The semiconductor integrated circuit has a substrate, a plurality of pads and a passivation layer. The pads are disposed on the substrate. The passivation layer extends over and covers a part of the substrate and a part of around each of the pads to define a plurality of openings, in which the conductive structure electrically connects to a corresponding pad of the pads through a corresponding opening of the openings. The conductive structure includes a buffering layer, an under bump metallurgy (UBM) layer and a bump. The buffering layer is formed on the passivation layer without fully blocking the corresponding opening. The UBM layer is substantially formed in the corresponding opening and electrically connects to the corresponding pad. Additionally, the UBM layer, formed under the bump, continuously extends over and covers a peripheral portion of the buffering layer.

摘要翻译： 提供了一种用于半导体集成电路的导电结构。 半导体集成电路具有基板，多个焊盘和钝化层。 焊盘设置在基板上。 钝化层延伸并覆盖衬底的一部分并且围绕每个衬垫的一部分以限定多个开口，其中导电结构通过开口的对应开口电连接到衬垫的相应衬垫。 导电结构包括缓冲层，凸块下金属（UBM）层和凸块。 缓冲层形成在钝化层上，而不完全阻挡相应的开口。 UBM层基本上形成在相应的开口中并且电连接到相应的垫。 此外，形成在凸块下方的UBM层连续地延伸并覆盖缓冲层的外围部分。

公开(公告)号：US20110298124A1

公开(公告)日：2011-12-08

申请号：US12899533

申请日：2010-10-06

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/498

CPC分类号： H01L23/49816 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/13083 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/13644 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29099 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2224/83097 ,  H01L2224/83192 ,  H01L2224/83204 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A semiconductor structure is provided. By using a composite bump with replace of a gold bump, the consumption of gold can be reduced and the manufacturing cost can be decreased accordingly. Moreover, by using an encapsulation material formed on a metal layer, the heat transferring efficiency of the semiconductor structure can be improved and the stability thereof can be increased.

摘要翻译： 提供半导体结构。 通过使用具有金凸块的复合凸块，可以减少黄金的消耗，并且可以相应地降低制造成本。 此外，通过使用形成在金属层上的封装材料，可以提高半导体结构的传热效率，并且可以提高其稳定性。

公开(公告)号：US20110183467A1

公开(公告)日：2011-07-28

申请号：US13082160

申请日：2011-04-07

申请人： Yu-Ren CHEN ,  Geng-Shin Shen ,  Tz-Cheng Chiu

发明人： Yu-Ren CHEN ,  Geng-Shin Shen ,  Tz-Cheng Chiu

IPC分类号： H01L21/56

CPC分类号： H01L21/561 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

摘要： A packaging method is disclosed that comprises attaching a plurality of dice, each having a plurality of bonding pads disposed on an active surface, to an adhesive layer on a substrate. A polymer material is formed over at least a portion of both the substrate and the plurality of dice and a molding apparatus is used on the substrate to force the polymer material to substantially fill around the plurality of dice. The molding apparatus is removed to expose a surface of the polymer material and a plurality of cutting streets is formed on an exposed surface of the polymer material. The substrate is removed to expose the active surface of the plurality of dice.

公开(公告)号：US07842550B2

公开(公告)日：2010-11-30

申请号：US12332362

申请日：2008-12-11

申请人： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

发明人： Chun-Ying Lin ,  Geng-Shin Shen ,  Po-Kai Hou

IPC分类号： H01L21/00

CPC分类号： H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of fabricating a quad flat non-leaded package includes first forming a patterned conductive layer on a sacrificial layer. The patterned conductive layer includes a number of lead sets. A number of chips are attached to the sacrificial layer. Each of the chips is surrounded by one of the lead sets. Each of the chips is electrically connected to one of the lead sets, and a molding compound is formed on the sacrificial layer to cover the patterned conductive layer and the chips. The molding compound and the patterned conductive layer are then cut and singulated, and the sacrificial layer is pre-cut to form a number of recesses on the sacrificial layer. After the molding compound and the patterned conductive layer are cut and singulated and the sacrificial layer is pre-cut, the sacrificial layer is removed.

摘要翻译： 制造四边形扁平非引线封装的方法包括首先在牺牲层上形成图案化的导电层。 图案化导电层包括多个引线组。 许多芯片附着到牺牲层。 每个芯片都被其中一个引线组包围。 每个芯片电连接到一个引线组，并且在牺牲层上形成模制化合物以覆盖图案化的导电层和芯片。 然后将成型化合物和图案化导电层切割并切割，并且牺牲层被预切割以在牺牲层上形成多个凹部。 在模制化合物和图案化的导电层被切割并切割并且牺牲层被预切割之后，去除牺牲层。

公开(公告)号：US07790514B2

公开(公告)日：2010-09-07

申请号：US12270627

申请日：2008-11-13

申请人： Geng-Shin Shen ,  Chun-Ying Lin

发明人： Geng-Shin Shen ,  Chun-Ying Lin

IPC分类号： H01L21/44

CPC分类号： H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/4951 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/73215 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer such that the first patterned solder resist layer is between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.

摘要翻译： 提供了一种用于芯片封装结构的制造工艺。 首先，提供在图案化导电层上具有多个第一开口和第一图案化阻焊层的图案化导电层。 在图案化导电层上形成第二图案化阻焊层，使得第一图案化阻焊层和第二图案化阻焊层设置在图案化导电层的两个相对表面处。 芯片被结合到第一图案化阻焊层上，使得第一图案化阻焊层位于芯片和图案化导电层之间。 芯片通过穿过第一开口的多个接合线电连接到图案化的导电层。 形成至少一种模塑料，并且分离模塑料，第一图案化阻焊层和第二图案化阻焊层。

公开(公告)号：US07786595B2

公开(公告)日：2010-08-31

申请号：US11826415

申请日：2007-07-16

申请人： Geng-Shin Shen ,  Wu-Chang Tu

发明人： Geng-Shin Shen ,  Wu-Chang Tu

IPC分类号： H01L23/48 ,  H01L23/495

CPC分类号： H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012

摘要： The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.

摘要翻译： 本发明提供了具有母线的引线框的芯片堆叠封装结构，包括：引线框架，由相互排列成行的多个内引线，多个外引线和管芯焊盘组成，其中管芯焊盘为 设置在所述多个内部引线之间并且与所述多个内部引线垂直; 芯片堆叠结构，形成有堆叠在一起并设置在芯片焊盘上的多个芯片，多个芯片和多个内部引线彼此电连接; 以及覆盖在所述芯片堆叠的封装结构和所述引线框架上的密封剂，其中所述引线框架至少包括汇流条，所述汇流条设置在彼此面对的所述多个排列成行的内引线和所述管芯焊盘之间。

公开(公告)号：US20090243056A1

公开(公告)日：2009-10-01

申请号：US12480105

申请日：2009-06-08

申请人： Wu-Chang Tu ,  Geng-Shin Shen

发明人： Wu-Chang Tu ,  Geng-Shin Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package having asymmetric molding includes a lead frame, a chip, an adhesive layer, bonding wires and a molding compound. The lead frame includes a turbulent plate and a frame body having inner lead portions and outer lead portions. The turbulent plate is bended downwards to form a concave portion. The first end of the turbulent plate is connected to the frame body, and the second end is lower than the inner lead portions. The chip is fixed under the inner lead portions through the adhesive layer. The bonding wires are connected between the chip and the inner lead portions. The molding compound encapsulates the chip, the bonding wires, and the turbulent plate. The ratio between the thickness of the molding compound over and under the concave portion is larger than 1. The thickness of the molding compound under and over the outer lead portions is not equal.

摘要翻译： 具有不对称模制的芯片封装包括引线框架，芯片，粘合剂层，接合线和模塑料。 引线框架包括湍流板和具有内引线部分和外引线部分的框体。 湍流板向下弯曲以形成凹部。 湍流板的第一端连接到框体，第二端低于内引线部。 芯片通过粘合剂层固定在内引线部分的下方。 接合线连接在芯片和内引线部分之间。 模塑料封装芯片，接合线和湍流板。 凹形部分上方和下方的模塑料的厚度之比大于1.外引线部分之下和之上的模塑料的厚度不相等。

公开(公告)号：US07538419B2

公开(公告)日：2009-05-26

申请号：US11684543

申请日：2007-03-09

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A stacked-type chip package structure including a substrate, a first chip, bonding wires, a second chip and B-stage conductive bumps is provided. The first chip is disposed on the substrate, and it has first bonding pads disposed on an active surface thereof. Besides, the first bonding pads are electrically connected to the substrate through the bonding wires. The second chip is disposed above the first chip, and it has second bonding pads disposed on an active surface thereof. The second bonding pads of the second chip are electrically connected to the first bonding pads of the first chip through the B-stage conductive bumps respectively, and each B-stage conductive bump covers a portion of the corresponding bonding wire.

摘要翻译： 提供了包括基板，第一芯片，接合线，第二芯片和B级导电凸块的堆叠型芯片封装结构。 第一芯片设置在基板上，并且其第一接合焊盘设置在其有效表面上。 此外，第一接合焊盘通过接合线电连接到基板。 第二芯片设置在第一芯片上方，并且其第二焊盘设置在其活性表面上。 第二芯片的第二焊盘分别通过B级导电凸块电连接到第一芯片的第一焊盘，并且每个B级导电凸块覆盖相应接合线的一部分。

公开(公告)号：US07504714B2

公开(公告)日：2009-03-17

申请号：US11351651

申请日：2006-02-10

申请人： Geng-Shin Shen

发明人： Geng-Shin Shen

IPC分类号： H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/4951 ,  H01L23/49551 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A chip package with asymmetric molding including a lead frame, a chip, an adhesive layer, bonding wires and an encapsulant, is provided. The lead frame includes a frame body and at least a turbulent plate. The frame body has inner lead portions and outer lead portions. The turbulent plate is bended upwards to form a bulge portion and the first end of the turbulent plate is connected to the frame body. The chip is fixed under the inner lead portions and the turbulent plate is located at one side of the chip. The adhesive layer is disposed between the chip and the inner lead portions, and the bonding wires are electrically connected between the chip and the corresponding inner lead portions, respectively. The encapsulant encapsulates at least the chip, the bonding wires, the inner lead portions, the adhesive layer and the turbulent plate.

摘要翻译： 提供具有不对称模制的芯片封装，包括引线框架，芯片，粘合剂层，接合线和密封剂。 引线框架包括框架体和至少湍流板。 框体具有内引线部和外引线部。 湍流板向上弯曲以形成凸起部分，并且湍流板的第一端连接到框架体。 芯片固定在内引线部分下方，湍流板位于芯片的一侧。 粘合剂层设置在芯片和内部引线部分之间，并且接合线分别电连接在芯片和对应的内部引线部分之间。 密封剂至少封装芯片，接合线，内引线部分，粘合剂层和湍流板。

公开(公告)号：US20090064494A1

公开(公告)日：2009-03-12

申请号：US12270666

申请日：2008-11-13

申请人： Geng-Shin Shen ,  Chun-Ying Lin

发明人： Geng-Shin Shen ,  Chun-Ying Lin

IPC分类号： H05K3/10

CPC分类号： H01L21/4857 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49558 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

摘要： A manufacturing process for a Quad Flat Non-leaded (QFN) chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned solder resist layer such that the patterned solder resist layer are between the chips and the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

摘要翻译： 提供了一种用于四边形扁平无铅（QFN）芯片封装结构的制造工艺。 首先，提供图案化导电层和图案化导电层上的图案化阻焊层。 多个芯片被结合到图案化的阻焊层上，使得图案化的阻焊层位于芯片和图案化的导电层之间。 芯片通过多根接合线与图案化导电层电连接，其中芯片和接合线位于图案化导电层的同一侧。 形成至少一种模塑料以封装图案化的导电层，图案化的阻焊层，芯片和接合线。 然后，分离模塑料，图案化导电层和图案化阻焊层。