公开(公告)号：US20050227432A1

公开(公告)日：2005-10-13

申请号：US11097404

申请日：2005-04-01

申请人： Jae-hyoung Choi ,  Sung-tae Kim ,  Ki-chul Kim ,  Cha-young Yoo ,  Jeong-hee Chung ,  Se-hoon Oh ,  Jeong-sik Choi

发明人： Jae-hyoung Choi ,  Sung-tae Kim ,  Ki-chul Kim ,  Cha-young Yoo ,  Jeong-hee Chung ,  Se-hoon Oh ,  Jeong-sik Choi

IPC分类号： H01L27/108 ,  H01L21/311 ,  H01L21/8242

CPC分类号： H01L21/31122

摘要： A metal-oxy-nitride seed dielectric layer can be formed on a metal-nitride lower electrode of a meta-insulator-metal (MIM) type capacitor. The metal-oxy-nitride seed dielectric layer can act as a barrier layer to reduce a reaction with the metal-nitride lower electrode during, for example, backend processing used to form upper levels of metallization/structures in an integrated circuit including the MIM type capacitor. Nitrogen included in the metal-oxy-nitride seed dielectric layer can reduce the type of reaction, which may occur in conventional type MIM capacitors. A metal-oxide main dielectric layer can be formed on the metal-oxy-nitride seed dielectric layer and can remain separate from the metal-oxy-nitride seed dielectric layer in the MIM type capacitor. The metal-oxide main dielectric layer can be stabilized (using, for example, a thermal or plasma treatment) to remove defects (such as carbon) therefrom and to adjust the stoichiometry of the metal-oxide main dielectric layer.

摘要翻译： 可以在间绝缘子金属（MIM）型电容器的金属氮化物下电极上形成金属 - 氮氧化物种子电介质层。 金属 - 氮化物种子电介质层可以用作阻挡层，以在例如用于在包括MIM型的集成电路中形成上层金属化/结构的后端处理中减少与金属氮化物下电极的反应 电容器。 包含在金属 - 氮氧化物种子电介质层中的氮可以减少在常规型MIM电容器中可能发生的反应类型。 可以在金属 - 氮化物种子介电层上形成金属氧化物主介电层，并且可以与MIM型电容器中的金属 - 氮化物种子电介质层保持分离。 金属氧化物主电介质层可以被稳定（使用例如热或等离子体处理）以从其中去除缺陷（例如碳）并调整金属氧化物主介电层的化学计量。

公开(公告)号：US07396719B2

公开(公告)日：2008-07-08

申请号：US10873256

申请日：2004-06-23

申请人： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

发明人： Kyoung-seok Kim ,  Hong-bae Park ,  Bong-hyun Kim ,  Sung-tae Kim ,  Jong-wan Kwon ,  Jung-hyun Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Gab-jin Nam ,  Young-sun Kim

IPC分类号： H01L21/471

CPC分类号： H01L21/0228 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/56 ,  H01L21/02175 ,  H01L21/02181 ,  H01L21/02205 ,  H01L21/3141 ,  H01L21/3142 ,  H01L21/3143 ,  H01L21/31645

摘要： A method of forming a high dielectric film using atomic layer deposition (ALD), and a method of manufacturing a capacitor having the high dielectric film, include supplying a precursor containing a metal element to a semiconductor substrate and purging a reactor; supplying an oxidizer and purging the reactor; and supplying a reaction source containing nitrogen and purging the reactor.

摘要翻译： 使用原子层沉积（ALD）形成高电介质膜的方法以及制造具有高电介质膜的电容器的方法包括将含有金属元素的前体供应到半导体衬底并清洗反应器; 供应氧化剂并清洗反应器; 并供应含氮的反应源并清洗反应器。

公开(公告)号：US07338861B2

公开(公告)日：2008-03-04

申请号：US11109749

申请日：2005-04-20

申请人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

发明人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

IPC分类号： H01L21/336

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42336

摘要： A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench. An inter-gate insulating layer is formed on the upper portion of floating gate and interposed between the floating gate and the control gate, and a drain region is formed in the surface of the substrate adjacent the control gate and spaced from the second sidewall of the trench.

摘要翻译： 提供一种非易失性存储器件，其包括浮置栅极，该浮置栅极具有形成在衬底表面中的沟槽中的下部，以及从下部突出到衬底表面上方的上部。 栅极绝缘层沿着沟槽的内壁形成并插入在沟槽和浮动栅极的下部之间。 源极区域形成在与沟槽的第一侧壁相邻的衬底中。 具有第一部分的控制栅极形成在邻近沟槽的第二侧壁的衬底的表面上方，并且第二部分形成在浮动栅极的上部并且从第一部分延伸。 沟槽的第一侧壁与沟槽的第二侧壁相对。 栅极间绝缘层形成在浮置栅极的上部并且插入在浮置栅极和控制栅极之间，并且漏极区域形成在基板的与控制栅极相邻的表面中并与第二侧壁间隔开 沟。

公开(公告)号：US08963580B2

公开(公告)日：2015-02-24

申请号：US13597732

申请日：2012-08-29

申请人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

发明人： Hyun-sik Choi ,  Ho-jung Kim ,  Ki-chul Kim ,  Jai-kwang Shin ,  Joong-ho Choi ,  Hyung-su Jeong

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/17756

摘要： A logic device may include a first functional block, the first functional block including, a first storage block, a second storage block, and a first function controller. In a first operation time period, the first function controller may be configured to receive a first configuration selection signal and a first configuration command signal that instructs a first function be configured, select the first storage block as a configured storage block in the first operation time period based on the first configuration selection signal, and configure the first function in the first storage block based on the first configuration command signal.

摘要翻译： 逻辑设备可以包括第一功能块，第一功能块包括第一存储块，第二存储块和第一功能控制器。 在第一操作时间段中，第一功能控制器可以被配置为接收第一配置选择信号和指示第一功能的第一配置命令信号，在第一操作时间中选择第一存储块作为配置的存储块 基于第一配置选择信号，并且基于第一配置命令信号来配置第一存储块中的第一功能。

公开(公告)号：US20120088360A1

公开(公告)日：2012-04-12

申请号：US13326700

申请日：2011-12-15

申请人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

发明人： Ki-chul Kim ,  Jong-cheol Lee ,  Heung-ahn Kwon ,  Hyun-wook Lee

IPC分类号： H01L21/28

CPC分类号： H01L21/28273 ,  H01L21/28282 ,  H01L27/10852 ,  H01L28/65 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/51 ,  H01L29/513

摘要： Methods of manufacturing a semiconductor device including a multi-layer of dielectric layers may include forming a metal oxide layer on a semiconductor substrate and forming a multi-layer of silicate layers including metal atoms and silicon atoms, on the metal oxide layer. The multi-layer of silicate layers may include at least two metallic silicate layers having different silicon concentrations, which are a ratio of silicon atoms among all metal atoms and silicon atoms included in the metallic silicate layer.

摘要翻译： 制造包括多层电介质层的半导体器件的方法可以包括在半导体衬底上形成金属氧化物层，并在金属氧化物层上形成包含金属原子和硅原子的多层硅酸盐层。 硅酸盐层的多层可以包括具有不同硅浓度的至少两个金属硅酸盐层，其是包含在金属硅酸盐层中的所有金属原子和硅原子之间的硅原子的比率。

公开(公告)号：US07202524B2

公开(公告)日：2007-04-10

申请号：US11061747

申请日：2005-02-22

申请人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

发明人： Ki-chul Kim ,  Young-cheon Jeong ,  Hyok-ki Kwon

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11553 ,  H01L29/42336

摘要： A nonvolatile memory device is provided which includes a floating gate having a lower portion formed in a trench defined in a surface of a substrate and an upper portion protruding above the surface of the substrate from the lower portion. A gate insulating layer is formed along an inner wall of the trench and interposed between the trench and the lower portion of the floating gate. A source region is formed in the substrate adjacent a first sidewall of the trench. A control gate having a first portion is formed over the surface of the substrate adjacent a second sidewall of the trench, and a second portion is formed over the upper portion of the floating gate and extending from the first portion. The first sidewall of the trench is opposite the second sidewall of the trench. An inter-gate insulating layer is formed on the upper portion of floating gate and interposed between the floating gate and the control gate, and a drain region is formed in the surface of the substrate adjacent the control gate and spaced from the second sidewall of the trench.

摘要翻译： 提供一种非易失性存储器件，其包括浮置栅极，该浮置栅极具有形成在衬底表面中的沟槽中的下部，以及从下部突出到衬底表面上方的上部。 栅极绝缘层沿着沟槽的内壁形成并插入在沟槽和浮动栅极的下部之间。 源极区域形成在与沟槽的第一侧壁相邻的衬底中。 具有第一部分的控制栅极形成在邻近沟槽的第二侧壁的衬底的表面上方，并且第二部分形成在浮动栅极的上部并且从第一部分延伸。 沟槽的第一侧壁与沟槽的第二侧壁相对。 栅极间绝缘层形成在浮置栅极的上部并且插入在浮置栅极和控制栅极之间，并且漏极区域形成在基板的与控制栅极相邻的表面中并与第二侧壁间隔开 沟。

公开(公告)号：US07144771B2

公开(公告)日：2006-12-05

申请号：US10616056

申请日：2003-07-09

申请人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

发明人： Gab-jin Nam ,  Seung-hwan Lee ,  Ki-chul Kim ,  Jae-soon Lim ,  Sung-tae Kim ,  Young-sun Kim

IPC分类号： H01L21/8242

CPC分类号： H01L21/02186 ,  C23C16/405 ,  H01L21/02183 ,  H01L21/02194 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Methods of forming an electronic device include providing a fist electrode, providing a dielectric oxide layer on the first electrode, and providing a second electrode on the dielectric oxide layer so that the dielectric oxide layer is between the first and second electrodes. More particularly, a first portion of the dielectric oxide layer adjacent the first electrode can have a first density of titanium, and a second portion of the dielectric oxide layer opposite the first electrode can have a second density of titanium different than the first density. Related structures are also discussed.

摘要翻译： 形成电子器件的方法包括提供第一电极，在第一电极上提供电介质氧化物层，并在电介质氧化物层上提供第二电极，使得电介质氧化物层位于第一和第二电极之间。 更具体地，与第一电极相邻的电介质氧化物层的第一部分可以具有第一密度的钛，并且与第一电极相对的电介质氧化物层的第二部分可具有不同于第一密度的钛的第二密度。 还讨论了相关结构。

公开(公告)号：US06893501B2

公开(公告)日：2005-05-17

申请号：US10320407

申请日：2002-12-17

申请人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

发明人： Ki-chul Kim ,  Sung-tae Kim ,  Young-sun Kim ,  Jeong-hee Chung ,  Wan-don Kim ,  Yun-jung Lee ,  Han-mei Choi

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/8242 ,  C30B25/04

CPC分类号： H01L28/57 ,  H01L21/02183 ,  H01L21/02271 ,  H01L21/02356 ,  H01L21/31637 ,  H01L27/1085 ,  H01L28/65

摘要： A method for manufacturing a capping layer covering a capacitor of a semiconductor memory device, preferably a metal-insulator-metal (MIM) capacitor, wherein the method includes forming a capacitor having a lower electrode, a dielectric layer and an upper electrode on a semiconductor substrate, forming a capping layer on the capacitor, and crystallizing the dielectric layer. Here, forming the capping layer includes stabilizing for deposition of the capping layer without providing oxygen gas, depositing the capping layer by providing a reaction source for the capping layer; and purging an inside of a reactor for forming the capping layer.

摘要翻译： 一种覆盖半导体存储器件的电容器，优选金属 - 绝缘体 - 金属（MIM）电容器的覆盖层的方法，其中所述方法包括在半导体上形成具有下电极，电介质层和上电极的电容器 衬底，在电容器上形成覆盖层，并使介电层结晶。 这里，形成覆盖层包括在不提供氧气的情况下沉积封盖层的稳定性，通过为封盖层提供反应源沉积覆盖层; 并且清洗用于形成覆盖层的反应器的内部。

公开(公告)号：US20090072350A1

公开(公告)日：2009-03-19

申请号：US12270286

申请日：2008-11-13

申请人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

发明人： Wan-don Kim ,  Jin-yong Kim ,  Yong-suk Tak ,  Jung-hee Chung ,  Ki-chul Kim ,  Oh-seong Kwon

IPC分类号： H01L29/92 ,  H01L21/20

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/60

摘要： Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes an insulating layer that is formed on a supporting layer and has a contact hole. A first contact plug is formed on an inner wall and bottom of the contact hole. A second contact plug buries the contact hole and is formed on the first contact plug. A conductive layer is connected to the first contact plug and the second contact plug. The bottom thickness of the first contact plug formed on the bottom of the contact hole is thicker than the inner wall thickness of the first contact plug formed on the inner wall of the contact hole.

摘要翻译： 提供半导体器件及其制造方法。 半导体器件包括形成在支撑层上并具有接触孔的绝缘层。 第一接触塞形成在接触孔的内壁和底部上。 第二接触插塞将接触孔埋入并形成在第一接触插塞上。 导电层连接到第一接触插塞和第二接触插塞。 形成在接触孔底部的第一接触塞的底部厚度比形成在接触孔的内壁上的第一接触塞的内壁厚度大。

公开(公告)号：US20080087967A1

公开(公告)日：2008-04-17

申请号：US11907106

申请日：2007-10-09

申请人： Ki-chul Kim

发明人： Ki-chul Kim

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7843

摘要： A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.

摘要翻译： 根据示例实施例的半导体器件可以包括具有NMOS区域和PMOS区域的衬底，形成在衬底中的隔离区域和阱区域，形成在隔离区域之间的衬底上的栅极图案，在衬底中形成的源极/漏极区域 源极/漏极区域中形成的栅极图案和隔离区域，源极/漏极硅化物区域，形成在NMOS区域上的拉伸应力层和形成在PMOS区域上的压应力层，其中拉伸应力层和压应力 层可以在NMOS区域和PMOS区域的边界区域处重叠。 根据示例性实施例的半导体器件及其制造方法可以增加对有源区域的应力作用，同时减少或防止对有源区域的表面损伤。