公开(公告)号：US06326255B1

公开(公告)日：2001-12-04

申请号：US09675053

申请日：2000-09-29

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

IPC分类号： H01L2126

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

公开(公告)号：US06289029B1

公开(公告)日：2001-09-11

申请号：US09160347

申请日：1998-09-25

申请人： Chiaki Goto ,  Hideo Miura

发明人： Chiaki Goto ,  Hideo Miura

IPC分类号： H01S310

CPC分类号： H01S3/042 ,  H01S3/025 ,  H01S3/0401 ,  H01S3/0405 ,  H01S3/0621 ,  H01S3/08031 ,  H01S3/09415 ,  H01S3/109

摘要： A solid state laser includes a solid state laser crystal, a pumping source for pumping the laser crystal, a resonator, an enclosed casing which is filled with gas and in which the resonator is contained, and a temperature controller which keeps the resonator at a predetermined temperature. The ratio of the optical length of the gas layer in the resonator to the oscillation wavelength of the solid state laser is set to be not larger than 13600.

摘要翻译： 固态激光器包括固体激光晶体，用于泵浦激光晶体的泵浦源，谐振器，填充有气体并且其中包含谐振器的封闭壳体以及将谐振器保持在预定的温度控制器 温度。 谐振器中的气体层的光学长度与固体激光器的振荡波长的比率被设定为不大于13600。

公开(公告)号：US06284625B1

公开(公告)日：2001-09-04

申请号：US09434308

申请日：1999-11-05

申请人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

发明人： Norio Ishitsuka ,  Hideo Miura ,  Shuji Ikeda ,  Yasuko Yoshida ,  Norio Suzuki ,  Michimasa Funabashi

IPC分类号： H01L2176

CPC分类号： H01L21/76224 ,  Y10S438/978

摘要： A method for manufacturing a semiconductor device includes the steps of (1) forming a pad oxide film of 5 nm or more on a circuit forming surface of a semiconductor substrate; (2) forming an oxidation inhibition film on the pad oxide film; (3) forming grooves of a given depth with the oxidation inhibition film as a mask; (4) receding the pad oxide film; (5) oxidizing the grooves formed on the semiconductor substrate in the range of 0

摘要翻译： 一种制造半导体器件的方法包括以下步骤：（1）在半导体衬底的电路形成表面上形成5nm以上的衬垫氧化膜; （2）在衬垫氧化膜上形成氧化抑制膜; （3）以氧化抑制膜为掩模形成给定深度的槽; （4）后退衬垫氧化膜; （5）在氧化气氛为干燥氧化（H2 /O2≈0）的0℃<0.88t-924的范围内对形成在半导体衬底上的沟槽进行氧化，对应于空气中的氧气分压 氧分压比为C％，氧化温度为t（℃）; （6）在氧化槽内埋入绝缘膜; （7）除去形成在氧化抑制膜上的埋置绝缘膜; （8）除去形成在半导体衬底的电路形成表面上的氧化抑制膜; 和（9）去除形成在所述半导体衬底的电路形成表面上的衬垫氧化膜。

公开(公告)号：US06211576B1

公开(公告)日：2001-04-03

申请号：US09397853

申请日：1999-09-17

申请人： Hiroya Shimizu ,  Asao Nishimura ,  Tosiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

发明人： Hiroya Shimizu ,  Asao Nishimura ,  Tosiho Miyamoto ,  Hideki Tanaka ,  Hideo Miura

IPC分类号： H01L2348

CPC分类号： H01L24/10 ,  H01L23/50 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

公开(公告)号：US06187100B1

公开(公告)日：2001-02-13

申请号：US09413890

申请日：1999-10-07

申请人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

发明人： Hideo Miura ,  Shunji Moribe ,  Hisayuki Kato ,  Atsuyoshi Koike ,  Shuji Ikeda ,  Asao Nishimura

IPC分类号： C23C1600

CPC分类号： H01L21/02667 ,  C23C16/24 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/52 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/28035 ,  H01L21/28525 ,  H01L21/28556 ,  H01L29/045 ,  H01L29/4916 ,  H01L29/66757 ,  H01L31/182 ,  H01L2924/0002 ,  Y02E10/546 ,  Y02P70/521 ,  H01L2924/00

摘要： A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

摘要翻译： 包含多晶硅薄膜的半导体器件可以通过沉积非杂质掺杂的硅薄膜来制造，其中硅薄膜的晶粒主要具有柱状结构和单个晶粒的晶体取向几乎是均匀的方向 或下层膜的界面上的杂质层，然后如果需要，沉积杂质掺杂的硅薄膜，然后进行多结晶热处理。

公开(公告)号：US5909052A

公开(公告)日：1999-06-01

申请号：US449722

申请日：1995-05-24

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Mitsuo Usami ,  Masatsugu Kametani ,  Munetoshi Zen ,  Noriaki Okamoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Mitsuo Usami ,  Masatsugu Kametani ,  Munetoshi Zen ,  Noriaki Okamoto

IPC分类号： G06F9/38 ,  G06F15/167 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06 ,  H01L29/04

CPC分类号： G06F9/3879 ,  G06F15/167 ,  G06F9/3877 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/95136 ,  H01L29/0657 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/351

摘要： Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated. If many kinds of semiconductor chips are prepared and connected in their combination in a variety of forms, it is possible to realize a many-kind small-amount production of semiconductor devices.

摘要翻译： 由于半导体芯片面积的增加，防止生产成品率的下降，可以制造精密性能的单芯片半导体器件。 这也允许实现多种少量的半导体器件的生产。 在单独制造多个半导体芯片2和3之后，仅选择它们的无缺陷芯片。 所选择的无缺陷芯片在它们的基板的最密实面的侧壁之间接触连接，使得要形成元件的表面4a和4b位于同一平面中。 因此，即使在芯片面积增加的情况下，也可以防止生产成品率的降低，从而可以制造大面积复杂性能的单芯片半导体器件。 如果准备多种半导体芯片并以各种形式组合连接，则可以实现多种少量的半导体器件的制造。

公开(公告)号：US5889312A

公开(公告)日：1999-03-30

申请号：US890997

申请日：1997-07-10

申请人： Hideo Miura ,  Yasunobu Tanizaki ,  Eiji Wakimoto ,  Shinji Sakata ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

发明人： Hideo Miura ,  Yasunobu Tanizaki ,  Eiji Wakimoto ,  Shinji Sakata ,  Makoto Ogasawara ,  Hiroo Masuda ,  Jun Murata ,  Noriaki Okamoto

IPC分类号： H01L21/762 ,  H01L27/08 ,  H01L3/22 ,  H01L21/265

CPC分类号： H01L21/76202 ,  H01L27/0802

摘要： A semiconductor device includes a thermal oxide film for isolation, a semiconductor region that becomes an element forming region with the circumference thereof surrounded by the oxide film and diffused resistance layers in the semiconductor region and provides a structure for controlling resistance value variation of diffused resistors originated in a stress generated at time of forming the oxide film for isolation. A distance between an end portion on a longer side closest to a thermal oxide film of the diffused layer and an end of the thermal oxide film is apart from each other by a predetermined value determined by stress distribution in the semiconductor region or by at least 4 .mu.m or more, the longitudinal direction of the diffused layer portion formed from the end of the thermal oxide film over to a stress distribution (gradient) forming region in the semiconductor region is parallel to the forming direction of the stress gradient, and resistance value distribution is formed parallel to the stress gradient in the diffused layer formed from the end of the thermal oxide film over to the stress distribution forming region in the semiconductor region.

摘要翻译： 半导体器件包括用于隔离的热氧化膜，半导体区域，其成为元件形成区域，其周边被半导体区域中的氧化物膜和扩散电阻层包围，并且提供用于控制起始的扩散电阻器的电阻值变化的结构 在形成用于隔离的氧化膜时产生的应力。 最靠近扩散层的热氧化膜的较长侧的端部与热氧化膜的端部之间的距离彼此分开由半导体区域中的应力分布确定的预定值或至少4 从热氧化膜的端部到半导体区域的应力分布（梯度）形成区域形成的扩散层部的纵向方向平行于应力梯度的形成方向，电阻值 分布形成为平行于从热氧化膜的端部到半导体区域中的应力分布形成区域形成的扩散层中的应力梯度。

公开(公告)号：US5402289A

公开(公告)日：1995-03-28

申请号：US996316

申请日：1992-12-23

申请人： Hideki Hayashi ,  Hideo Miura ,  Seilichi Funaya ,  Kouji Seki

发明人： Hideki Hayashi ,  Hideo Miura ,  Seilichi Funaya ,  Kouji Seki

IPC分类号： G11B15/44 ,  G11B5/54

CPC分类号： G11B15/442

摘要： A mode plate (5) which moves between a plurality of operational positions controls the respective positions of a head plate (2) and a link (8). The link (8) is turned to a forward and a reverse position to selectively operate pinch roller casings (12F, 12R) through a change link (4). This causes pinch rollers (13F, 13R) to be pressed against capstans (15F, 15R), respectively to thereby provide a forward or reverse play mode tape travel. By the turning of the link (8), an FF/REW plate (27) is moved to a forward and a reverse side through a detect link (9) and a spring (9a) such that FF/REW gears (25F, 25R) supported at the ends of an FF/REW plate (27) engage selectively with reel bases (11F, 11R) to thereby perform tape travel in an FF mode or a REW mode. A head plate (2) controls the positions of pinch roller casings (12F, 12R) and the FF/REW plate (27). At a stop mode position, the head plate (2) holds the pinch roller casings (12F, 12R) and FF/REW plate (27) at the release positions while holding the FF/REW plate (27) at the release position at a play mode position. The head plate (29) causes idler plates (26F, 26R) which support idler gears (24F, 24R) to engage pinch roller casings (12F, 12R) to operate the idler plates (26F, 26R) depending on the operation of the pinch roller casings (12F, 12R) and engages the idler gears (24F, 24R) selectively with reel bases (11F, 11R), respectively.

摘要翻译： 在多个操作位置之间移动的模板（5）控制头板（2）和连杆（8）的各自位置。 连杆（8）转向正向和反向位置，以通过变速杆（4）选择性地操作压紧辊壳体（12F，12R）。 这使得夹送辊（13F，13R）分别压靠在绞盘（15F，15R）上，从而提供正向或反向播放模式的磁带行进。 通过连杆（8）的转动，通过检测连杆（9）和弹簧（9a）将FF / REW板（27）移动到前侧和后侧，使得FF / REW齿轮（25F，25R ）支撑在FF / REW板（27）的端部，其选择性地与卷轴基座（11F，11R）接合，从而以FF模式或REW模式执行磁带行进。 头板（2）控制压紧辊壳体（12F，12R）和FF ​​/ REW板（27）的位置。 在停止模式位置，头板（2）将夹紧辊壳体（12F，12R）和FF ​​/ REW板（27）保持在释放位置，同时将FF / REW板（27）保持在释放位置处 播放模式位置。 头板（29）引起支撑惰轮（24F，24R）的惰轮板（26F，26R），以接合夹紧辊壳体（12F，12R），以根据夹紧件的操作来操作惰轮板（26F，26R） 辊筒（12F，12R）分别与空转齿轮（24F，24R）分别与卷盘底座（11F，11R）啮合。

公开(公告)号：US4987474A

公开(公告)日：1991-01-22

申请号：US536932

申请日：1990-06-12

申请人： Toshihiro Yasuhara ,  Masachika Masuda ,  Asao Nishimura ,  Naozumi Hatada ,  Sueo Kawai ,  Makoto Kitano ,  Hideo Miura ,  Akihiro Yaguchi ,  Gen Murakami

发明人： Toshihiro Yasuhara ,  Masachika Masuda ,  Asao Nishimura ,  Naozumi Hatada ,  Sueo Kawai ,  Makoto Kitano ,  Hideo Miura ,  Akihiro Yaguchi ,  Gen Murakami

IPC分类号： H01L23/495

CPC分类号： H01L24/32 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49558 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351

摘要： In a tabless lead frame wherein a space for laying inner leads is sufficiently secured when a lengthened and enlarged semiconductor pellet is placed or set in a resin-molding package, through holes are provided in leads for the purpose of increasing the occupation area ratio of a resin portion. Furthermore, each of the leads corresponding to the lower surface of the pellet is branched into a plurality of portions in the widthwise direction thereof in order to reduce a stress. Further, in an insulating sheet which is interposed between the leads and the pellet, the dimension of the shorter lateral sides thereof is set smaller than that of the shorter lateral sides of the pellet in order to prevent cracks from occurring at the end part of the insulating sheet.

摘要翻译： 在放置或放置在树脂成型包装体中的放大或放大的半导体芯片时，用于放置内部引线的空间被充分地固定的无引线框架中，为了增加占空比的目的，提供通孔 树脂部分。 此外，与颗粒的下表面相对应的每个引线在其宽度方向上分支成多个部分，以便减小应力。 此外，在介于引线和芯片之间的绝缘片中，其较短侧面的尺寸被设定为小于颗粒的较短侧面的尺寸，以防止在端部的端部发生裂纹 绝缘片。

公开(公告)号：US08026609B2

公开(公告)日：2011-09-27

申请号：US12759335

申请日：2010-04-13

申请人： Tomio Iwasaki ,  Hideo Miura

发明人： Tomio Iwasaki ,  Hideo Miura

IPC分类号： H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53252 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided, is a reliable semiconductor device with a layered interconnect structure that may develop no trouble of voids and interconnect breakdowns, in which the layered interconnect structure comprises a conductor film and a neighboring film as so layered on a semiconductor substrate that the neighboring film is contacted with the conductor film. In the device, the materials for the conductor film and the neighboring film are so selected that the difference between the short side, ap, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the short side, an, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lap−anl/ap}×100=A (%) and the difference between the long side, bp, of the rectangular unit cells that constitute the plane with minimum free energy of the conductor film and the long side, bn, of the rectangular unit cells that constitute the plane with minimum free energy of the neighboring film, {lbp−bnl/bp}×100=B (%) satisfy an inequality of {A+B×(ap/bp)}

摘要翻译： 提供的是具有分层互连结构的可靠的半导体器件，其可以不产生空隙和互连故障的问题，其中分层互连结构包括导体膜和相邻的膜，如此分层在半导体衬底上，邻近膜被接触 与导体膜。 在该器件中，用于导体膜和相邻膜的材料被选择成使得构成具有导体膜的最小自由能和短边的平面的矩形单位电池的短边面ap之间的差， ，构成相邻膜的最小自由能的平面的矩形单位电池，构成的矩形单位电池的长边，bp之间的差值，即（lap-anl / ap}×100 = A（％） 构成相邻膜的最小自由能的{B1p-bnl / bp}×100 = B（％）的平面的矩形单位电池的导体膜的最小自由能和长边bn的平面满足 {A + B×（ap / bp）} <13的不等式。 在此，导体膜的扩散被延迟。