公开(公告)号：US20140332936A1

公开(公告)日：2014-11-13

申请号：US13889370

申请日：2013-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Gottfried Beer ,  Dominic Maier ,  Ulrich Wachter ,  Daniel Kehrer

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L23/552 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/3128 ,  H01L24/18 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/00

Abstract: In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure.

Abstract translation: 在各种实施例中，可以提供包装布置。 封装结构可以包括至少一个芯片。 封装结构还可以包括至少部分地封装芯片的封装材料。 封装布置还可以包括在芯片的第一侧上的再分布结构。 封装布置还可以包括在芯片的第二侧上的金属结构。 第二面可以与第一面相对。 封装结构可以另外包括半导体结构和导电塑料材料结构中的至少一个，该结构电耦合到再分布结构和金属结构，以形成再分布结构和金属结构之间的电流路径。

公开(公告)号：US20140310671A1

公开(公告)日：2014-10-16

申请号：US13863740

申请日：2013-04-16

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Dominic Maier ,  Gerhard Metzger-Brückl ,  Rainer Leuschner

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5081

Abstract: The capacitance or inductance of electrical circuits is adjusted by measuring inductance or capacitance values of passive components fabricated on a first substrate, storing individual associations between the passive components and the respective measured values of the passive components, and determining electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components. A corresponding system includes a tester operable to measure inductance or capacitance values of the passive components fabricated on the first substrate, a storage system operable to store the individual associations between the passive components and the respective measured values of the passive components, and a processing circuit operable to determine the electrical connections for the passive components based on the stored individual associations between the passive components and the respective measured values of the passive components.

Abstract translation: 通过测量在第一基板上制造的无源部件的电感或电容值来调节电路的电容或电感，存储无源元件之间的各个关联以及无源元件的相应测量值，以及确定基于无源元件的电连接 关于无源部件之间存储的各个关联以及被动部件的相应测量值。 相应的系统包括可操作以测量制造在第一基板上的无源部件的电感或电容值的测试器，可操作以存储无源部件之间的各个关联和无源部件的相应测量值的存储系统，以及处理电路 可操作以基于所存储的无源组件之间的各个关联和无源组件的相应测量值来确定无源组件的电连接。

公开(公告)号：US20140206109A1

公开(公告)日：2014-07-24

申请号：US13745550

申请日：2013-01-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Ossimitz ,  Matthias von Daak ,  Gottfried Beer

IPC: H01L21/66

CPC classification number: H01L22/10 ,  G01R31/2884 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A method of producing and testing a chip package is described. The chip package to be produced includes a semiconductor chip containing an integrated circuit and a reinforcing structure attached to the semiconductor chip. Further, the chip package has a lower main face and an upper main face opposite to the lower main face, wherein the lower main face is at least partly formed by an exposed surface of the semiconductor chip and the upper main face is formed by a terminal surface of the reinforcing structure on which external terminal pads of the chip package are arranged. After production, the package is subjected to a package-level burn-in test.

Abstract translation: 描述了制造和测试芯片封装的方法。 要制造的芯片封装包括一个包含集成电路的半导体芯片和一个附着在半导体芯片上的加强结构。 此外，芯片封装具有与下主面相对的下主面和上主面，其中下主面至少部分地由半导体芯片的暴露表面形成，并且上主面由终端形成 所述加强结构的表面布置有所述芯片封装的外部端子焊盘。 生产后，对包装进行封装级老化测试。

公开(公告)号：US08786085B2

公开(公告)日：2014-07-22

申请号：US13671573

申请日：2012-11-08

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Barth ,  Mathias Vaupel ,  Rainer Steiner ,  Werner Robl ,  Jens Pohl ,  Joern Plagmann ,  Gottfried Beer

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76807 ,  H01L21/76879 ,  H01L23/49816 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/0106 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00

Abstract: One or more embodiments relate to a semiconductor structure, comprising: a barrier layer overlying a workpiece surface; a seed layer overlying the barrier layer; an inhibitor layer overlying said seed layer, the inhibitor layer having a opening exposing a portion of the seed layer, and a fill layer overlying the exposed portion of the seed layer.

Abstract translation: 一个或多个实施例涉及半导体结构，包括：覆盖工件表面的阻挡层; 覆盖阻挡层的种子层; 覆盖所述种子层的抑制剂层，所述抑制剂层具有暴露所述种子层的一部分的开口以及覆盖所述种子层的暴露部分的填充层。

公开(公告)号：US20140070913A1

公开(公告)日：2014-03-13

申请号：US14024395

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Urs Elrod ,  Christiane Brunner ,  Thomas Kilger

IPC: H01F27/28 ,  H01F41/04

CPC classification number: H01F27/2804 ,  H01F41/041 ,  H01F2027/2819 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/645 ,  H01L24/19 ,  H01L2224/12105 ,  Y10T29/4902 ,  Y10T29/49071

Abstract: In accordance with an embodiment, a transformer includes a first coil disposed in a first conductive layer on a first side of a first dielectric layer, and a second coil disposed in a second conductive layer on a second side of the first dielectric layer. Each coil has a first end disposed inside its respective coil and a second end disposed at an outer perimeter of its respective coil. A first crossover disposed in the second conductive layer is directly connected to the first end of the first coil and extends past the outer perimeter of the first coil. In addition, a second crossover disposed in the first conductive layer is directly connected to the first end of the second coil and extends past the outer perimeter of the second coil.

Abstract translation: 根据实施例，变压器包括设置在第一电介质层的第一侧上的第一导电层中的第一线圈和设置在第一电介质层的第二侧上的第二导电层中的第二线圈。 每个线圈具有设置在其相应线圈内部的第一端和设置在其相应线圈的外周边的第二端。 设置在第二导电层中的第一交叉直接连接到第一线圈的第一端并且延伸超过第一线圈的外周。 此外，设置在第一导电层中的第二交叉直接连接到第二线圈的第一端并且延伸超过第二线圈的外周。

公开(公告)号：US10522433B2

公开(公告)日：2019-12-31

申请号：US15487942

申请日：2017-04-14

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Horst Theuss ,  Gottfried Beer

IPC: H01L23/051 ,  H01L23/06 ,  H01L21/48 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/13 ,  H01L23/14 ,  H01L23/488 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46

Abstract: A package which comprises a chip carrier made of a first material, a body made of a second material differing from the first material and being arranged on the chip carrier so as to form a cavity, a semiconductor chip arranged at least partially in the cavity, and a laminate encapsulating at least one of at least part of the chip carrier, at least part of the body and at least part of the semiconductor chip.

公开(公告)号：US10295570B2

公开(公告)日：2019-05-21

申请号：US14837048

申请日：2015-08-27

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Wolfgang Furtner

IPC: G01R15/14 ,  G01R19/00 ,  G01R1/20 ,  G01R19/32

Abstract: The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.

公开(公告)号：US09984928B2

公开(公告)日：2018-05-29

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/44 ,  H01L21/78 ,  H01L21/66 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.

公开(公告)号：US09818730B2

公开(公告)日：2017-11-14

申请号：US14477386

申请日：2014-09-04

Applicant: Infineon Technologies AG

Inventor： Gottfried Beer ,  Irmgard Escher-Poeppel ,  Juergen Hoegerl ,  Olaf Hohlfeld ,  Peter Kanschat

IPC: H01L23/48 ,  H01L25/07 ,  H01L23/492 ,  H01L23/495 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/051 ,  H01L23/31

CPC classification number: H01L25/072 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/051 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/492 ,  H01L23/49562 ,  H01L23/562 ,  H01L24/24 ,  H01L24/33 ,  H01L24/72 ,  H01L24/82 ,  H01L24/83 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/03002 ,  H01L2224/06181 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/29011 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/83801 ,  H01L2224/8384 ,  H01L2224/8385 ,  H01L2224/96 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/2064 ,  H01L2924/20643 ,  H01L2924/20644 ,  H01L2224/03 ,  H01L2224/82 ,  H01L2924/00

Abstract: A semiconductor arrangement includes top and bottom contact plates, a plurality of chip assemblies, a dielectric embedding compound, and a control electrode interconnection structure. Each chip assembly has a semiconductor chip having a semiconductor body. The semiconductor body has a top side and an opposing underside. The top side is spaced apart from the underside in a vertical direction. Each semiconductor chip has a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, a control electrode arranged at the top side, and an electrically conductive top compensation die, arranged on the side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode by means of a top connecting layer. An electric current between the top main electrode and the bottom main electrode can be controlled by means of the control electrode.

公开(公告)号：US20170098580A1

公开(公告)日：2017-04-06

申请号：US15378669

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Gottfried Beer ,  Edward Fuergut ,  Juergen Hoegerl ,  Peter Kanschat

IPC: H01L21/78 ,  H01L21/56 ,  H01L21/48 ,  H01L21/66

CPC classification number: H01L21/78 ,  H01L21/4875 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L22/10 ,  H01L22/14 ,  H01L23/051 ,  H01L23/31 ,  H01L23/522 ,  H01L24/96 ,  H01L25/072 ,  H01L25/115 ,  H01L27/02 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/2518 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: Method for producing chip assemblies that include semiconductor chip arrangements, each semiconductor chip arrangement including a semiconductor chip having a semiconductor body with a top side and an underside, a top main electrode arranged on the top side, a bottom main electrode arranged on the underside, an electrically conductive top compensation lamina arranged on a side of the top main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the top main electrode, an electrically conductive bottom compensation lamina arranged on a side of the bottom main electrode facing away from the semiconductor body and cohesively and electrically conductively connected to the bottom main electrode, and a dielectric embedding compound enclosing the semiconductor chip laterally such that the side of the compensation laminae facing away from the semiconductor body are at least not completely covered by the embedding compound.