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    Disabling a command associated with a memory device
    21.
    发明授权
    Disabling a command associated with a memory device 有权
    禁用与存储设备关联的命令

    公开(公告)号：US09213491B2

    公开(公告)日：2015-12-15

    申请号：US14230338

    申请日：2014-03-31

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Kuljit S. Bains

    IPC: G06F12/00 ,  G06F13/00 ,  G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0608 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0634 ,  G06F3/0673 ,  G06F3/068 ,  G06F11/2094 ,  G06F2201/805 ,  G11C7/1045 ,  G11C7/24 ,  G11C29/025 ,  G11C29/46 ,  G11C29/50012 ,  G11C29/70 ,  G11C29/76 ,  G11C29/83

    Abstract: In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation of the memory device. A field in the mode register may hold a value that may indicate whether a command associated with the memory device is disabled. The value may be held in the field until either the memory device is power-cycled or reset. The device processing logic may acquire an instance of the command. The device processing logic may determine whether the command is disabled based on the value held by the mode register. The device processing logic may not execute the instance of the command if the device processing logic determines the command is disabled. If the device processing logic determines the command is not disabled, the device processing logic may execute the instance of the command.

    Abstract translation: 在一个实施例中，存储器设备可以包含设备处理逻辑和模式寄存器。 模式寄存器可以是可以指定存储器件的操作模式的寄存器。 模式寄存器中的字段可以保存可以指示与存储器设备相关联的命令是否被禁用的值。 该值可以保持在现场，直到存储器件被上电或复位为止。 设备处理逻辑可以获取命令的实例。 设备处理逻辑可以基于模式寄存器保持的值来确定该命令是否被禁用。 如果设备处理逻辑确定该命令被禁用，则设备处理逻辑可能不执行该命令的实例。 如果设备处理逻辑确定命令未被禁止，则设备处理逻辑可以执行该命令的实例。

    INTERFERENCE TESTING
    22.
    发明申请
    INTERFERENCE TESTING 有权
    干扰测试

    公开(公告)号：US20150280781A1

    公开(公告)日：2015-10-01

    申请号：US14229460

    申请日：2014-03-28

    Applicant: Intel Corporation

    Inventor： Alexey Kostinsky ,  Tomer Levy ,  Paul S. Cheses ,  Danny Naiger ,  Theodore Z. Schoenborn ,  Christopher P. Mozak ,  Nagi Aboulenien ,  James M. Shehadi

    IPC: H04B3/46

    CPC classification number: H04B3/487 ,  G01R31/28 ,  G01R31/31855 ,  G06F11/00

    Abstract: In one example a controller comprises logic, at least partially including hardware logic, configured to implement a first iteration of an interference test on a communication interconnect comprising a victim lane and a first aggressor lane by generating a first set of pseudo-random patterns on the victim lane and the aggressor lane using a first seed and implement a second iteration of an interference test by advancing the seed on the first aggressor lane. Other examples may be described.

    Abstract translation: 在一个示例中，控制器包括至少部分地包括硬件逻辑的逻辑，其被配置为通过在第一组伪随机模式上产生第一组伪随机模式来实现在包括受害者通道和第一侵入者通道的通信互连上的干扰测试的第一次迭代 受害者车道和侵略者车道，并通过在第一侵略者车道上推进种子来实施干扰测试的第二次迭代。 可以描述其他示例。

    Refresh rate performance based on in-system weak bit detection
    23.
    发明授权
    Refresh rate performance based on in-system weak bit detection 有权
    基于系统弱位检测的刷新率性能

    公开(公告)号：US09076499B2

    公开(公告)日：2015-07-07

    申请号：US13730413

    申请日：2012-12-28

    Applicant: Intel Corporation

    Inventor： Theodore Z. Schoenborn ,  Christopher P. Mozak

    IPC: G06F11/00 ,  G11C7/02 ,  G11C11/406 ,  G11C29/02 ,  G11C29/50 ,  G11C11/40

    CPC classification number: G11C7/02 ,  G11C11/40 ,  G11C11/40611 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50016 ,  G11C2211/4062

    Abstract: A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.

    Abstract translation: 存储器子系统可以原位测试存储器件，测试在生产过程中内置的系统中的器件的性能。 因此，可以将特定系统的存储设备的刷新速率特定地调整，而不是默认为由存储设备的标准指定的刷新频率。 嵌入主机存储器子系统中的测试组件可以执行测试并识别当使用较低频率刷新率时产生错误的特定位或存储器行。 系统映射标识的位或行，以防止在系统运行时使用位/线。 存储器子系统然后可以将其刷新速率设置为调整后的刷新速率，通过映射比特/行可以消除阈值数量的错误。

    Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals
    24.
    发明授权
    Training for command/address/control/clock delays under uncertain initial conditions and for mapping swizzled data to command/address signals 有权
    在不确定的初始条件下对指令/地址/控制/时钟延迟进行训练，并将旋转数据映射到命令/地址信号

    公开(公告)号：US09026725B2

    公开(公告)日：2015-05-05

    申请号：US13728581

    申请日：2012-12-27

    Applicant: Intel Corporation

    Inventor： Alexey Kostinsky ,  Zvika Greenfield ,  Christopher P. Mozak ,  Pavel Konev ,  Olga Fomenko

    IPC: G11C7/10 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02

    CPC classification number: G11C7/1072 ,  G11C7/1063 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/105 ,  G11C2207/2254

    Abstract: Data pin mapping and delay training techniques. Valid values are detected on a command/address (CA) bus at a memory device. A first part of the pattern (high phase) is transmitted via a first subset of data pins on the memory device in response to detecting values on the CA bus; a second part of the pattern (low phase) is transmitted via a second subset of data pins on the memory device in response to detecting values on the CA bus. Signals are sampled at the memory controller from the data pins while the CA pattern is being transmitted to obtain a first memory device's sample (high phase) and the second memory device's sample (low phase) by analyzing the first and the second subset of sampled data pins. The analysis combined with the knowledge of the transmitted pattern on the CA bus leads to finding the unknown data pins mapping. Varying the transmitted CA patterns and the resulting feedbacks sampled on memory controller data signals allows CA/CTRL/CLK signals delay training with and without priory data pins mapping knowledge.

    Abstract translation: 数据引脚映射和延迟训练技术。 在存储设备的命令/地址（CA）总线上检测到有效值。 响应于CA总线上的检测值，该模式的第一部分（高相位）经由存储器件上的数据引脚的第一子集传输; 响应于CA总线上的检测值，经由数据引脚的第二子集在存储器件上传送图案（低相位）的第二部分。 信号在存储器控制器处被从数据引脚采样，同时正在发送CA模式，以通过分析采样数据的第一和第二子集来获得第一存储器件的采样（高相位）和第二存储器件的采样（低相位） 针脚。 分析结合CA总线上传输模式的知识，找到未知的数据引脚映射。 改变传输的CA模式和在存储器控制器数据信号上采样的结果反馈允许CA / CTRL / CLK信号延迟训练，并且不使用二进制数据引脚映射知识。

    Power efficient, single-ended termination using on-die voltage supply
    25.
    发明授权
    Power efficient, single-ended termination using on-die voltage supply 有权
    使用片上电压供电的功率高效，单端端接

    公开(公告)号：US08929157B2

    公开(公告)日：2015-01-06

    申请号：US13680604

    申请日：2012-11-19

    Applicant: Intel Corporation

    Inventor： Christopher P. Mozak ,  Navindra Navaratnam ,  Mahmoud Elassal

    IPC: G11C7/00 ,  G05F1/10 ,  G11C5/14

    CPC classification number: G05F1/10 ,  G11C5/145 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/105 ,  H02M3/07 ,  H02M2003/1566

    Abstract: Circuitry to provide a supply voltage. A voltage regulator is coupled to receive a target reference signal. The voltage regulator generates a supply voltage (Vtt) and is coupled to receive the supply voltage as an input signal. An upper limit comparator receives an upper limit voltage signal that is higher than the target reference voltage signal and the supply voltage to generate a “too high” signal when the supply voltage exceeds an upper threshold. A lower limit comparator receives a lower limit voltage signal that is lower than the target reference voltage signal and the supply voltage to generate a “too low” signal when the supply voltage is below a lower threshold. A pull up current source is coupled to pull the supply voltage up in response to the too low signal. A pull down current source is coupled to pull the supply voltage down in response to the too high signal.

    Abstract translation: 电路提供电源电压。 电压调节器被耦合以接收目标参考信号。 电压调节器产生电源电压（Vtt）并被耦合以接收电源电压作为输入信号。 当电源电压超过上限阈值时，上限比较器接收高于目标参考电压信号和电源电压的上限电压信号，以产生“过高”信号。 下限比较器接收低于目标参考电压信号的下限电压信号和电源电压，以在电源电压低于下阈值时产生“太低”信号。 耦合上拉电流源以响应于太低的信号将电源电压拉高。 耦合下拉电流源以响应于太高的信号而将电源电压降低。

    Efficiently training memory device chip select control
    28.
    发明授权
    Efficiently training memory device chip select control 有权

    公开(公告)号：US11061590B2

    公开(公告)日：2021-07-13

    申请号：US16547197

    申请日：2019-08-21

    Applicant: Intel Corporation

    Inventor： Tonia G. Morris ,  Christopher P. Mozak ,  Christopher E. Cox

    IPC: G06F3/06 ,  G11C11/4076 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02

    Abstract: A chip select training mode (CSTM) enables a memory subsystem to train a chip select signal separately from command bus training. A memory device and a memory controller can connect via a command bus including a chip select signal line. Instead of training the chip select along with other signal lines of the command bus, a CSTM mode enables the memory subsystem to more accurately train the chip select. The memory device can be triggered for CSTM mode with a command, and then train voltage margining for the CS signal line to align chip select signaling with the memory subsystem clock signal.

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