公开(公告)号：US20180226496A1

公开(公告)日：2018-08-09

申请号：US15771998

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Van H. LE ,  Matthew V. METZ ,  Seiyon KIM ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/267 ,  H01L29/10 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/30625 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/107 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7854

Abstract: A transistor having an ultra thin fin profile and its method of fabrication is described. The transistor comprises a semiconductor substrate having an insulation layer formed on a semiconductor substrate. A fin extends from the semiconductor substrate. The fin has a subfin portion on the semiconductor substrate and an active fin portion on the subfin portion. The subfin portion is disposed in a trench formed in the insulation layer. The subfin portion comprises a III-V semiconductor material and the active fin portion comprises a group IV semiconductor material.

公开(公告)号：US20180204947A1

公开(公告)日：2018-07-19

申请号：US15570742

申请日：2015-06-16

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Van H. LE ,  Ravi PILLARISETTY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7851 ,  H01L21/02639 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/785

Abstract: A subfin layer is deposited in a trench in an insulating layer on the substrate. A fin is deposited on the subfin layer. The fin has a top portion and opposing sidewalls. The fin comprises a first semiconductor material. The subfin layer comprises a III-V semiconductor material.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US20170012125A1

公开(公告)日：2017-01-12

申请号：US15119345

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Van H. LE ,  Benjamin CHU-KUNG ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Ravi PILLARISETTY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Robert S. CHAU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823885 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

Abstract translation: 描述用于制造垂直半导体器件和纵向半导体器件的纵横比捕获（ART）方法。 例如，半导体器件包括具有第一晶格常数的最上表面的衬底。 第一源极/漏极区域设置在衬底的最上表面上并且具有第二不同的晶格常数。 垂直沟道区域设置在第一源极/漏极区域上。 第二源极/漏极区域设置在垂直沟道区域上。 栅堆叠设置在垂直沟道区的一部分上并完全环绕。

公开(公告)号：US20160211263A1

公开(公告)日：2016-07-21

申请号：US14915185

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niti GOEL ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract translation: 从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。 翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。 翅片高度可以是其宽度的至少1.5倍。 暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。 在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。 翅片的这种形成减少了材料界面晶格失配的缺陷。

公开(公告)号：US20160204208A1

公开(公告)日：2016-07-14

申请号：US14778574

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Niti GOEL ,  Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew V. METZ ,  Marko RADOSAVLJEVIC ,  Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Robert S. CHAU

IPC: H01L29/205 ,  H01L29/06 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract translation: 第一种基于III-V材料的缓冲层沉积在硅衬底上。 第二个III-V材料的缓冲层沉积在第一个III-V材料的缓冲层上。 在基于第二III-V材料的缓冲层上沉积基于III-V材料的器件沟道层。

公开(公告)号：US20230420511A1

公开(公告)日：2023-12-28

申请号：US17850623

申请日：2022-06-27

Applicant: Intel Corporation

Inventor： Carl H. NAYLOR ,  Kirby MAXEY ,  Kevin P. O'BRIEN ,  Chelsey DOROW ,  Sudarat LEE ,  Ashish Verma PENUMATCHA ,  Uygar E. AVCI ,  Matthew V. METZ ,  Scott B. CLENDENNING ,  Chia-Ching LIN ,  Carly ROGAN ,  Arnab SEN GUPTA

IPC: H01L29/06 ,  H01L29/778 ,  H01L29/786 ,  H01L29/18 ,  H01L21/02

CPC classification number: H01L29/0673 ,  H01L29/778 ,  H01L29/78696 ,  H01L21/02568 ,  H01L21/02645 ,  H01L21/02598 ,  H01L21/02485 ,  H01L29/18

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for a transistor structure that includes stacked nanoribbons as a single crystal or monolayer, such as a transition metal dichalcogenide (TMD) layer, grown on a silicon wafer using a seeding material. Other embodiments may be described and/or claimed.

公开(公告)号：US20230006065A1

公开(公告)日：2023-01-05

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Willy RACHMADY ,  Jack T. KAVALIEROS ,  Cheng-Ying HUANG ,  Matthew V. METZ ,  Sean T. MA ,  Harold KENNEL ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US20220102522A1

公开(公告)日：2022-03-31

申请号：US17033499

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Nazila HARATIPOUR ,  Siddharth CHOUKSEY ,  Arnab SEN GUPTA ,  Christopher J. JEZEWSKI ,  I-Cheng TUNG ,  Matthew V. METZ ,  Anand S. MURTHY

IPC: H01L29/45 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/08 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66

Abstract: Low resistance and reduced reactivity approaches for fabricating contacts, and semiconductor structures having low resistance metal contacts, are described. In an example, an integrated circuit structure includes a semiconductor structure above a substrate. A gate electrode is over the semiconductor structure, the gate electrode defining a channel region in the semiconductor structure. A first semiconductor source or drain structure is at a first end of the channel region at a first side of the gate electrode. A second semiconductor source or drain structure is at a second end of the channel region at a second side of the gate electrode, the second end opposite the first end. A source or drain contact is on the first or second semiconductor source or drain structure, the source or drain contact including an alloyed metal barrier layer and an inner conductive structure.

公开(公告)号：US20210242325A1

公开(公告)日：2021-08-05

申请号：US17236338

申请日：2021-04-21

Applicant: INTEL CORPORATION

Inventor： Gilbert DEWEY ,  Mark L. DOCZY ,  Suman DATTA ,  Justin K. BRASK ,  Matthew V. METZ

IPC: H01L29/51 ,  H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed.