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21.发明申请Methods And Apparatuses For Reducing Power Consumption Of Processor Switch Operations 审中-公开降低处理器开关操作功耗的方法和装置公开(公告)号：US20160004533A1
公开(公告)日：2016-01-07
申请号：US14854082
申请日：2015-09-15
Applicant: INTEL CORPORATION
Inventor： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
CPC classification number: G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US08994344B2
公开(公告)日：2015-03-31
申请号：US13727227
申请日：2012-12-26
Applicant: Intel Corporation
Inventor： Gerhard Schrom , Peter Hazucha , Jaeseo Lee , Tanay Karnik , Vivek K. De , Fabrice Paillet
Abstract: A multiphase DC-DC converter is provided that includes a multiphase transformer, the multiphase transformer including a plurality of input voltage terminals and an transformer output voltage terminal, each input voltage terminal associated with a corresponding phase. Each phase is assigned to an input voltage terminal of the plurality of input voltage terminals to minimize a ripple current at the input voltage terminals of the multiphase transformer.
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23.发明授权公开(公告)号：US08824198B2
公开(公告)日：2014-09-02
申请号：US13906230
申请日：2013-05-30
Applicant: Intel Corporation
Inventor： Vivek K. De , DiaaEidin S. Khalil , Muhammad M. Khellah , Moty Mehalel , George Shchupak
IPC: G11C11/00 , G11C11/412
CPC classification number: G11C5/142 , G11C5/063 , G11C11/412 , G11C11/413
Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.
Abstract translation: 采用共享供电结构的寄存器文件来提高最小电源电压。
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公开(公告)号：US10984855B2
公开(公告)日：2021-04-20
申请号：US16285057
申请日：2019-02-25
Applicant: Intel Corporation
Inventor： Jaydeep P. Kulkarni , Bibiche M. Geuskens , James Tschanz , Vivek K. De , Muhammed M. Khellah
IPC: G11C11/419 , G11C5/14 , G11C7/12 , G11C8/10 , H01L27/11 , G11C7/08 , G11C11/4074 , G11C11/412 , G11C11/417 , G11C11/418 , G11C13/00 , G11C29/02 , G11C8/08
Abstract: Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
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公开(公告)号：US10024916B2
公开(公告)日：2018-07-17
申请号：US15422392
申请日：2017-02-01
Applicant: INTEL CORPORATION
Inventor： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC: G01R31/3177 , G01R31/317
Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
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Patent Agency Ranking
公开(公告)号：US20170139006A1
公开(公告)日：2017-05-18
申请号：US15422392
申请日：2017-02-01
Applicant: INTEL CORPORATION
Inventor： Keith A. Bowman , James W. Tschanz , Nam Sung Kim , Janice C. Lee , Christopher B. Wilkerson , Shih-Lien L. Lu , Tanay Karnik , Vivek K. De
IPC: G01R31/3177 , G01R31/317
CPC classification number: G01R31/3177 , G01R31/31723 , G01R31/31725 , G01R31/31727 , G06F1/10 , G06F11/0706 , G06F11/0757 , G06F11/0793 , H03K3/0375
Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
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公开(公告)号：US20170041001A1
公开(公告)日：2017-02-09
申请号：US15331280
申请日：2016-10-21
Applicant: INTEL CORPORATION
Inventor： Arijit Raychowdhury , Charles Augustine , James W. Tschanz , Vivek K. De
CPC classification number: H03K19/0016 , G05F1/10 , G05F1/461 , G05F1/59 , G06F1/3287 , G06F1/3296 , H03K3/0377 , H03K19/0008
Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply, the clamp including a plurality of transistors, a circuit to operate with the second power supply; and a control unit to turn on and off the plurality of transistors to adjust the second power supply when the apparatus enters a low power mode. The control unit includes a first comparator to compare the second power supply with a first reference, a second comparator to compare the second power supply with a second reference, and a counter. The counter counts up when the second power supply is higher than the first reference and counts down when the second power supply is lower than the second reference.
Abstract translation: 描述了一种装置，其包括：夹紧器，其耦合在第一电源和第二电源之间，所述夹具包括多个晶体管，用于与所述第二电源一起操作的电路; 以及控制单元，用于在所述设备进入低功率模式时接通和断开所述多个晶体管以调节所述第二电源。 控制单元包括用于将第二电源与第一参考值进行比较的第一比较器，将第二电源与第二参考电压进行比较的第二比较器和计数器。 当第二电源高于第一个参考电压时，计数器递增计数，当第二个电源低于第二个参考电压时，计数器递减计数。
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公开(公告)号：US20160170456A9
公开(公告)日：2016-06-16
申请号：US13626357
申请日：2012-09-25
Applicant: INTEL CORPORATION
Inventor： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC: G06F1/26 , G06F1/32 , H01L25/065
CPC classification number: G06F1/26 , G06F1/3206 , G06F1/324 , G06F1/3296 , H01L23/34 , H01L24/16 , H01L25/0657 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06589 , Y02D10/126 , Y02D10/172
Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
Abstract translation: 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。
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29.发明授权Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power mode 有权用于指定和保存寄存器子集的单个指令，指定在唤醒后执行的工作监视功能的指针，以及进入低功耗模式公开(公告)号：US09164764B2
公开(公告)日：2015-10-20
申请号：US14286536
申请日：2014-05-23
Applicant: INTEL CORPORATION
Inventor： Ethan Schuchman , Hong Wang , Chris Weaver , Belliappa M. Kuttanna , Asit Mallick , Vivek K. De , Per Hammarlund
CPC classification number: G06F9/30083 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/324 , G06F1/3246 , G06F1/3265 , G06F1/3268 , G06F1/3296 , G06F9/30043 , G06F9/30105 , G06F9/3012 , G06F9/3013 , G06F9/461 , Y02D10/126 , Y02D10/128 , Y02D10/153 , Y02D10/154 , Y02D10/172 , Y02D50/20
Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.
Abstract translation: 公开了用于降低处理器开关操作功耗的方法和装置。 一个或多个实施例可以包括指定要参与寄存器或状态存储操作的寄存器或状态存储元件的子集，执行寄存器或状态存储操作，以及执行开关操作。 这些实施例可以通过仅指定寄存器或状态存储元件的子集来最小化与备用操作相关的寄存器或状态存储元件的数量，其可能涉及明显少于处理器的寄存器或状态存储器或元件的总数量。 切换操作可以从一种模式切换到另一种模式，例如转换到睡眠模式，上下文切换或各种类型的指令的执行。
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公开(公告)号：US20150241890A1
公开(公告)日：2015-08-27
申请号：US13976223
申请日：2012-09-25
Applicant: Intel Corporation
Inventor： Arijit Raychowdhury , Dinesh Somasekhar , James W. Tschanz , Vivek K. De
CPC classification number: G05F1/577 , G05F1/468 , G05F1/56 , G06F1/06 , G06F1/26 , H03L7/085 , Y10T307/406
Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.
Abstract translation: 描述了一种装置，包括：第一振荡器，用于产生第一时钟信号第二振荡器以产生第二时钟信号; 相位频率检测器，用于检测第一和第二时钟信号之间的相位差，并产生相位差; 以及耦合到负载的输出级，以根据相位差产生用于负载的电源。
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