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公开(公告)号：US08524528B2
公开(公告)日：2013-09-03
申请号：US13725574
申请日：2012-12-21
Applicant: Intermolecular Inc.
Inventor： Sean Barstow , Tony Chiang , Pragati Kumar , Sandra Malhotra
CPC classification number: H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641
Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.
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22.发明申请公开(公告)号：US20130125923A1
公开(公告)日：2013-05-23
申请号：US13738112
申请日：2013-01-10
Applicant: Intermolecular Inc.
Inventor： Anh Duong , Sean Barstow , Olov Karlsson , Bei Li , James Mavrinac
IPC: H01L21/02
CPC classification number: H01L21/02052 , H01L21/02068 , H01L21/28518 , H01L29/665
Abstract: A method for cleaning platinum residues from a surface of a substrate is provided. The method initiates with exposing the surface to a first solution containing a mixture of nitric acid and hydrochloric acid. Then, the surface is exposed to a second solution containing hydrochloric acid.
Abstract translation: 提供了从基板的表面清除铂残留物的方法。 该方法首先将表面暴露于含有硝酸和盐酸混合物的第一溶液。 然后，将表面暴露于含有盐酸的第二溶液。
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公开(公告)号：US09297775B2
公开(公告)日：2016-03-29
申请号：US14285921
申请日：2014-05-23
Applicant: Intermolecular Inc.
Inventor： Edwin Adhiprakasha , Sean Barstow , Ashish Bodke , Zhendong Hong , Usha Raghuram , Karthik Ramani , Vivian Ryan , Jingang Su , Xunyuan Zhang
CPC classification number: G01N27/20 , C23C14/06 , C23C14/14 , C23C14/3464 , C23C14/54 , C23C14/548 , G01N27/041
Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.
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公开(公告)号：US20150338362A1
公开(公告)日：2015-11-26
申请号：US14285921
申请日：2014-05-23
Applicant: Intermolecular Inc.
Inventor： Edwin Adhiprakasha , Sean Barstow , Ashish Bodke , Zhendong Hong , Usha Raghuram , Karthik Ramani , Vivian Ryan , Jingang Su , Xunyuan Zhang
CPC classification number: G01N27/20 , C23C14/06 , C23C14/14 , C23C14/3464 , C23C14/54 , C23C14/548 , G01N27/041
Abstract: Barrier layers, barrier stacks, and seed layers for small-scale interconnects (e.g., copper) are combinatorially screened using test structures sputtered or co-sputtered through apertures of varying size. Various characteristics (e.g., resistivity, crystalline morphology, surface roughness) related to conductivity, diffusion blocking, and adhesion are measured before and/or after annealing and compared to arrive at materials and process parameters for low diffusion with high conductivity through the interconnect. Example results show that some formulations of tantalum-titanium barriers may replace thicker tantalum/tantalum-nitride stacks, in some cases with a Cu—Mn seed layer between the Ta—Ti and copper.
Abstract translation: 使用通过不同大小的孔溅射或共溅射的测试结构组合地筛选用于小规模互连（例如铜）的阻挡层，阻挡层和种子层。 在退火之前和/或之后测量与导电性，扩散阻挡和粘附有关的各种特性（例如，电阻率，结晶形态，表面粗糙度）并进行比较以获得材料和工艺参数，以通过互连实现高导电性的低扩散。 示例结果表明，一些钽 - 钛屏障的配方可以替代较厚的钽/氮化钽叠层，在某些情况下可以在Ta-Ti和铜之间具有Cu-Mn种子层。
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公开(公告)号：US08889547B2
公开(公告)日：2014-11-18
申请号：US14045100
申请日：2013-10-03
Applicant: Intermolecular Inc.
Inventor： Sean Barstow , Owen Ho Yin Fong
IPC: H01L21/44 , H01L21/768 , C23C14/04 , C23C14/34
CPC classification number: H01L21/76867 , C23C14/042 , C23C14/3464
Abstract: Provided are methods and systems for forming discreet multilayered structures. Each structure may be deposited by in situ deposition of multiple layers at one of multiple site isolation regions provided on the same substrate for use in combinatorial processing. Alignment of different layers within each structure is provided by using two or more differently sized openings in-between one or more sputtering targets and substrate. Specifically, deposition of a first layer is performed through the first opening that defines a first deposition area. A shutter having a second smaller opening is then positioned in-between the one or more targets and substrate. Sputtering of a second layer is then performed through this second opening that defines a second deposition area. This second deposition area may be located within the first deposition area based on sizing and alignment of the openings as well as alignment of the substrate.
Abstract translation: 提供形成谨慎的多层结构的方法和系统。 每个结构可以通过在设置在同一基底上的多个位置隔离区域之一的原位沉积多层来沉积，以用于组合处理。 通过在一个或多个溅射靶和衬底之间使用两个或更多个不同尺寸的开口来提供每个结构内的不同层的对准。 具体地，通过限定第一沉积区域的第一开口进行第一层的沉积。 然后将具有第二较小开口的闸板定位在一个或多个目标和基板之间。 然后通过限定第二沉积区域的该第二开口进行第二层的溅射。 基于开口的尺寸和对准以及衬底的对准，该第二沉积区域可以位于第一沉积区域内。
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Patent Agency Ranking
公开(公告)号：US20140273309A1
公开(公告)日：2014-09-18
申请号：US14051287
申请日：2013-10-10
Applicant: Intermolecular, Inc.
Inventor： Sandip Niyogi , Sean Barstow , Jay Dedontney , Chi-I Lang , Ratsamee Limdulpaiboon , Martin Romero , Sunil Shanker , James Tsung , J. Watanabe
CPC classification number: H01L21/30 , B01J19/0046 , B01J2219/00283 , B01J2219/00286 , B01J2219/00301 , B01J2219/00313 , B01J2219/0038 , B01J2219/00382 , B01J2219/00416 , B01J2219/00418 , B01J2219/00527 , B01J2219/00585 , B08B3/04 , C23C14/08 , C23C14/22 , C23C14/34 , C23C18/1619 , C23C18/1682 , C25D17/02 , G11C13/0004 , H01L21/02104 , H01L21/30604 , H01L21/67051 , H01L21/67057 , H01L21/6719 , H01L22/10 , H01L22/12 , H01L22/14 , H01L27/2463 , H01L45/1608
Abstract: Remote-plasma treatments of surfaces, for example in semiconductor manufacture, can be improved by preferentially exposing the surface to only a selected subset of the plasma species generated by the plasma source. The probability that a selected species reaches the surface, or that an unselected species is quenched or otherwise converted or diverted before reaching the surface, can be manipulated by introducing additional gases with selected properties either at the plasma source or in the process chamber, varying chamber pressure or flow rate to increase or decrease collisions, or changing the dimensions or geometry of the injection ports, conduits and other passages traversed by the species. Some example processes treat surfaces preferentially with relatively low-energy radicals, vary the concentration of radicals at the surface in real time, or clean and passivate in the same unit process.
Abstract translation: 可以通过优选地将表面暴露于由等离子体源产生的等离子体物质的选定子集中来改善表面的远程等离子体处理，例如在半导体制造中。 所选择的物种到达表面的可能性，或未被选择的物质在到达表面之前被淬灭或以其他方式转化或转移的可能性可以通过在等离子体源或处理室，变化室中引入具有选定性质的附加气体来操纵 压力或流量以增加或减少碰撞，或改变注射口，管道和由物种穿过的其它通道的尺寸或几何形状。 一些示例性过程优先用相对低能量的基团处理表面，实时地改变表面处的自由基的浓度，或者在相同的单元过程中清洁和钝化。
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公开(公告)号：US20140264281A1
公开(公告)日：2014-09-18
申请号：US14137183
申请日：2013-12-20
Applicant: Intermolecular, Inc.
Inventor： Sandip Niyogi , Sean Barstow , Chi-I Lang , Ratsamee Limdulpaiboon , Dipankar Pramanik , J. Watanabe
CPC classification number: H01L21/76864 , H01L21/02005 , H01L21/02104 , H01L21/02172 , H01L21/02175 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02205 , H01L21/0228 , H01L21/283 , H01L21/28575 , H01L21/3065 , H01L22/12 , H01L22/14 , H01L27/1462 , H01L27/14643 , H01L27/14698 , H01L29/1606 , H01L29/41 , H01L29/66477 , H01L29/66742 , H01L29/778 , H01L29/786
Abstract: Semiconductor devices and methods of making thereof are disclosed. A field effect transistor (FET) is provided comprising a substrate, a first layer disposed above the substrate, the first layer being operable as a gate electrode, a second layer disposed above the first layer, the second layer comprising a dielectric material, a third layer disposed above the second layer, the third layer comprising a semiconductor, and a fourth layer comprising one or more conductive materials and operable as source and drain electrodes disposed above the third layer. In some embodiments, the dielectric material comprises a high-κ dielectric. In some embodiments, the source and drain electrodes comprise one or more metals. The source and drain electrodes are each in ohmic contact with an area of the top surface of the third layer, and substantially all of the current through the transistor flows through the ohmic contacts.
Abstract translation: 公开了半导体器件及其制造方法。 提供场效应晶体管（FET），其包括基板，设置在基板上方的第一层，第一层可操作为栅电极，第二层设置在第一层上方，第二层包括电介质材料，第三层 层，其设置在所述第二层上方，所述第三层包括半导体，以及包括一个或多个导电材料并可操作为设置在所述第三层上方的源极和漏极的第四层。 在一些实施例中，电介质材料包括高压 电介质。 在一些实施例中，源电极和漏电极包括一种或多种金属。 源电极和漏电极各自与第三层的顶表面的区域欧姆接触，并且基本上所有通过晶体管的电流都流经欧姆接触。
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公开(公告)号：US20130323863A1
公开(公告)日：2013-12-05
申请号：US13726834
申请日：2012-12-26
Applicant: Intermolecular, Inc.
Inventor： Sandip Niyogi , Sean Barstow
IPC: H01L21/02
CPC classification number: H01L21/02527 , B82Y30/00 , B82Y40/00 , C01B32/184 , C23C14/042 , C23C14/0605 , C23C14/185 , C23C14/5806 , H01L21/02422 , H01L21/02672 , H01L21/32051 , H01L21/76823 , H01L23/53276 , H01L2924/0002 , H01L2924/00
Abstract: A method for depositing graphene is provided. The method includes depositing a layer of non-conducting amorphous carbon over a surface of a substrate and depositing a transition metal in a pattern over the amorphous carbon. The substrate is annealed at a temperature below 500° C., where the annealing converts the non-conducting amorphous carbon disposed under the transition metal to conducting amorphous carbon. A portion of the pattern of the transition metal is removed from the surface of the substrate to expose the conducting amorphous carbon.
Abstract translation: 提供了一种沉积石墨烯的方法。 该方法包括在衬底的表面上沉积非导电无定形碳层并且以无定型碳上的图案沉积过渡金属。 将衬底在低于500℃的温度下退火，其中退火将设置在过渡金属下面的非导电非晶碳转化成导电无定形碳。 过渡金属的图案的一部分从衬底的表面去除以暴露导电无定形碳。
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公开(公告)号：US08599603B2
公开(公告)日：2013-12-03
申请号：US13829378
申请日：2013-03-14
Applicant: Intermolecular Inc.
Inventor： Pragati Kumar , Sean Barstow , Tony P. Chiang , Sandra G Malhotra
IPC: G11C11/00
CPC classification number: H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以形成在集成电路上的一个或多个层中。 每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。 诸如二极管的电气设备可以与存储器元件串联耦合。 第一导电层可以由金属氮化物形成。 金属氧化物层可以包含与第一导电层相同的金属。 金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。 第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。 第一导电层，金属氧化物层和第二导电层可以包括子层。 第二导电层可以包括粘合或阻挡层和功函数控制层。
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公开(公告)号：US20130059427A1
公开(公告)日：2013-03-07
申请号：US13656585
申请日：2012-10-19
Applicant: Intermolecular, Inc.
Inventor： Sandra G. Malhotra , Sean Barstow , Tony P. Chiang , Pragati Kumar , Prashant B. Phatak , Sunil Shanker , Wen Wu
IPC: H01L21/02
CPC classification number: H01L45/1608 , H01L27/2418 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1625 , H01L45/1641
Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.
Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。
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