公开(公告)号：US20160141256A1

公开(公告)日：2016-05-19

申请号：US15003820

申请日：2016-01-22

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/00 ,  H01L21/288 ,  H01L23/495 ,  H01L21/78

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

公开(公告)号：US20150137305A1

公开(公告)日：2015-05-21

申请号：US14566751

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

IPC: H01L27/02 ,  H01L29/868 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

Abstract: Described herein is a protective structure. The protective structure includes a semiconductor substrate, a first diode disposed at least one of in or on the semiconductor substrate and a diode arrangement disposed at least one of in or on the semiconductor substrate. The diode arrangement includes a stack of a second diode and a transient voltage suppressor (TVS) diode connected in series with the second diode. The diode arrangement is in parallel with the first diode.

Abstract translation: 这里描述的是保护结构。 保护结构包括半导体衬底，设置在半导体衬底中或半导体衬底中的至少一个上的第一二极管和设置在半导体衬底中或半导体衬底中的至少之一上的二极管布置。 二极管装置包括与第二二极管串联连接的第二二极管和瞬态电压抑制器（TVS）二极管的堆叠。 二极管布置与第一二极管并联。

公开(公告)号：US20150069591A1

公开(公告)日：2015-03-12

申请号：US14023493

申请日：2013-09-11

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L27/0248 ,  H01L21/288 ,  H01L21/7685 ,  H01L21/78 ,  H01L21/784 ,  H01L23/4827 ,  H01L23/495 ,  H01L23/522 ,  H01L23/544 ,  H01L23/562 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L24/98 ,  H01L2223/5446 ,  H01L2224/04026 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/0569 ,  H01L2224/2746 ,  H01L2224/2747 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2916 ,  H01L2224/29164 ,  H01L2224/29166 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/10337 ,  H01L2924/1037 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2224/27 ,  H01L2924/0781 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: According to various embodiments, a method for manufacturing a semiconductor device may include providing a semiconductor workpiece including a device region at a first side of the semiconductor workpiece, wherein a mechanical stability of the semiconductor workpiece is insufficient to resist at least one back end process without damage, and depositing at least one conductive layer over a second side of the semiconductor workpiece opposite the first side of the semiconductor workpiece, wherein the at least one conductive layer increases the mechanical stability of the semiconductor workpiece to be sufficient to resist the at least one back end process without damage.

Abstract translation: 根据各种实施例，半导体器件的制造方法可以包括提供半导体工件，其包括在半导体工件的第一侧的器件区域，其中半导体工件的机械稳定性不足以抵抗至少一个后端工艺，而没有 损坏，并且在半导体工件的与半导体工件的第一侧相对的第二侧上沉积至少一个导电层，其中至少一个导电层增加半导体工件的机械稳定性，以足以抵抗至少一个 后端程序无损坏。

公开(公告)号：US12009361B2

公开(公告)日：2024-06-11

申请号：US18100043

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Joost Willemen ,  Andre Schmenn ,  Damian Sojka

IPC: H01L27/06 ,  H01L27/02 ,  H01L29/66 ,  H01L29/732 ,  H01L29/74 ,  H01L29/861

CPC classification number: H01L27/067 ,  H01L27/0262 ,  H01L29/6609 ,  H01L29/861 ,  H01L29/66371 ,  H01L29/732 ,  H01L29/7404

Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.

公开(公告)号：US11929305B2

公开(公告)日：2024-03-12

申请号：US17532446

申请日：2021-11-22

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Klaus Diefenbeck ,  Joost Adriaan Willemen

IPC: H01L23/48 ,  H01L21/822 ,  H01L23/482 ,  H01L27/02 ,  H01L21/56

CPC classification number: H01L23/4825 ,  H01L21/822 ,  H01L27/0292 ,  H01L21/56 ,  H01L27/0255

Abstract: In a method for manufacturing an electrostatic discharge protection circuit, an electrostatic discharge device structure is formed during a front side processing of a semiconductor substrate in a first area. Contact pads are formed on the front side on the electrostatic discharge device structure and in a second area. During back side processing of the semiconductor substrate, a metal connection between the first electrostatic discharge device structure and the second area is formed.

公开(公告)号：US11916059B2

公开(公告)日：2024-02-27

申请号：US17411060

申请日：2021-08-25

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

IPC: H01L23/60 ,  H01L27/02 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

CPC classification number: H01L27/0248 ,  H01L21/78 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/60 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/072 ,  H01L25/50 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0292 ,  H01L29/7416 ,  H02H9/04 ,  H01L27/0744 ,  H01L29/74 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2924/1203 ,  H01L2924/1301 ,  H01L2924/30205 ,  H01L2924/1301 ,  H01L2924/00012 ,  H01L2924/1203 ,  H01L2924/00012

Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

公开(公告)号：US10672758B2

公开(公告)日：2020-06-02

申请号：US15787124

申请日：2017-10-18

Applicant: Infineon Technologies AG

Inventor： Vadim Valentinovic Vendt ,  Stefan Pompl ,  Andre Schmenn ,  Joost Willemen

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/06 ,  H01L29/87 ,  H01L29/74

Abstract: According an embodiment, an electrostatic discharge protection structure includes: a semiconductor layer doped with a dopant of a first doping type, a first well region extending from a surface of the semiconductor layer into the semiconductor layer, wherein the first well region is doped with a dopant of a second doping type opposite the first doping type; a second well region next to the first well region and extending from the surface of the semiconductor layer into the semiconductor layer, wherein the second well region is doped with a dopant of the first doping type; an isolation structure extending from the surface of the semiconductor layer into the semiconductor layer with a depth similar to the depth of at least one of the first well region or the second well region, wherein the isolation structure is arranged laterally adjacent to the first well region and the second well region.

公开(公告)号：US09966277B2

公开(公告)日：2018-05-08

申请号：US15361108

申请日：2016-11-25

Applicant: Infineon Technologies AG

Inventor： Markus Zundel ,  Andre Schmenn ,  Damian Sojka ,  Isabella Goetz ,  Gudrun Stranzl ,  Sebastian Werner ,  Thomas Fischer ,  Carsten Ahrens ,  Edward Fuergut

IPC: H01L21/78 ,  H01L21/56 ,  H01L23/498 ,  H01L27/02 ,  H01L23/31 ,  H01L29/861

CPC classification number: H01L21/561 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/49838 ,  H01L27/0248 ,  H01L27/0255 ,  H01L29/861 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a substrate having a front side and a back side, a die region within the substrate, a multi-purpose layer defining a back side of the die region, and an etch stop layer disposed over the multi-purpose layer between the multi-purpose layer and the back side of the substrate. The multi-purpose layer may be formed of an ohmic material, and the etch stop layer may be of a first conductivity type of a first doping concentration.

公开(公告)号：US20160149021A1

公开(公告)日：2016-05-26

申请号：US14552567

申请日：2014-11-25

Applicant: Infineon Technologies AG

Inventor： Andre Schmenn ,  Damian Sojka

IPC: H01L29/74 ,  H01L27/02 ,  H01L29/66

CPC classification number: H01L29/66371 ,  H01L21/28562 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/7412

Abstract: A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.

Abstract translation: 根据各种实施例的垂直集成的半导体器件可以包括：第一半导体层; 设置在所述第一半导体层上的第二半导电层; 设置在所述第二半导体层上的第三半导体层; 以及耦合在所述第一半导体层和所述第二半导体层之间的电旁路。

公开(公告)号：US09196568B2

公开(公告)日：2015-11-24

申请号：US14042750

申请日：2013-10-01

Applicant: Infineon Technologies AG

Inventor： Thomas Fischer ,  Carsten Ahrens ,  Damian Sojka ,  Andre Schmenn ,  Edward Fuergut

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/3114 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/00

Abstract: An arrangement is provided. The arrangement may include: a die including at least one electronic component and a first terminal on a first side of the die and a second terminal on a second side of the die opposite the first side, wherein the first side being the main processing side of the die, and the die further including at least a third terminal on the second side; a first electrically conductive structure providing current flow from the third terminal on second side of the die to the first side through the die; a second electrically conductive structure on the first side of the die laterally coupling the second terminal with the first electrically conductive structure; and an encapsulation material disposed at least over the first side of the die covering the first terminal and the second electrically conductive structure.

Abstract translation: 提供了一种安排。 该装置可以包括：模具，其包括至少一个电子部件和在模具的第一侧上的第一端子，以及在模具的与第一侧相对的第二侧上的第二端子，其中第一侧是主要处理侧 所述管芯和所述管芯还包括在所述第二侧上的至少第三端子; 第一导电结构，其提供从模具的第二侧上的第三端子到通过模具的第一侧的电流; 在所述模具的第一侧上的第二导电结构将所述第二端子与所述第一导电结构横向地联接; 以及封装材料，其至少设置在覆盖所述第一端子和所述第二导电结构的所述管芯的所述第一侧的上方。