公开(公告)号：US20180166625A1

公开(公告)日：2018-06-14

申请号：US15882546

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

公开(公告)号：US09882123B2

公开(公告)日：2018-01-30

申请号：US15333017

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  G11C11/16 ,  H01L27/22 ,  H01F10/193 ,  H01L43/02

CPC classification number: H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

公开(公告)号：US09496486B2

公开(公告)日：2016-11-15

申请号：US14812655

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

公开(公告)号：US09478734B2

公开(公告)日：2016-10-25

申请号：US14723310

申请日：2015-05-27

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Uday Shah ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  Mark L. Doczy ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  G11C11/18 ,  H01L27/22 ,  H01F10/193

CPC classification number: H01L43/10 ,  G11C11/161 ,  G11C11/18 ,  H01F10/14 ,  H01F10/16 ,  H01F10/1936 ,  H01F10/3236 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/226 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability are described. For example, a material layer stack for a magnetic tunneling junction includes a fixed magnetic layer. A dielectric layer is disposed above the fixed magnetic layer. A free magnetic layer is disposed above the dielectric layer. A conductive oxide material layer is disposed on the free magnetic layer.

公开(公告)号：US09472748B2

公开(公告)日：2016-10-18

申请号：US14992601

申请日：2016-01-11

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Brian S. Doyle ,  Arijit Raychowdhury ,  Roksana Golizadeh Mojarad ,  Kaan Oguz

IPC: G11C11/00 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/08 ,  H01L43/12

Abstract: Techniques are disclosed for enhancing performance of a perpendicular magnetic tunnel junction (MTJ) by implementing an additional ferromagnetic layer therein. The additional ferromagnetic layer can be implemented, for example, in or otherwise proximate either the fixed ferromagnetic layer or the free ferromagnetic layer of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is implemented with a non-magnetic spacer, wherein the thickness of the additional ferromagnetic layer and/or spacer can be adjusted to sufficiently balance the energy barrier between parallel and anti-parallel states of the perpendicular MTJ. In some embodiments, the additional ferromagnetic layer is configured such that its magnetization is opposite that of the fixed ferromagnetic layer.

公开(公告)号：US09455343B2

公开(公告)日：2016-09-27

申请号：US14040574

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/66 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

Abstract translation: 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

公开(公告)号：US20160190282A1

公开(公告)日：2016-06-30

申请号：US15062007

申请日：2016-03-04

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Uday Shah ,  Roza Kotlyar ,  Charles C. Kuo

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/205 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L29/10

CPC classification number: H01L29/66666 ,  H01L21/02532 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4983 ,  H01L29/66356 ,  H01L29/66363 ,  H01L29/7391 ,  H01L29/749 ,  H01L29/7827 ,  H01L29/7848

Abstract: Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region disposed on a substrate, an epitaxial channel semiconductor region disposed on the source semiconductor region, an epitaxial drain semiconductor region disposed on the channel semiconductor region, and a gate electrode region surrounding sidewalls of the semiconductor channel region. A composition of at least one of the semiconductor regions varies along a longitudinal axis that is perpendicular with respect to a surface of the substrate.

公开(公告)号：US09293560B2

公开(公告)日：2016-03-22

申请号：US14534088

申请日：2014-11-05

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Roza Kotlyar ,  Uday Shah ,  Charles C. Kuo

IPC: H01L21/336 ,  H01L29/66 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract translation: 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US09231194B2

公开(公告)日：2016-01-05

申请号：US13996603

申请日：2013-03-28

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Elijah V. Karpov ,  Roksana Golizadeh Mojarad ,  David L. Kencke ,  Robert S. Chau

IPC: H01L43/10 ,  G11C11/16 ,  H01L43/12 ,  H01L43/08 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01L43/065 ,  H01L43/08 ,  H01L43/12 ,  H01L43/14

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; the tunnel barrier directly contacting a first side of the free layer; and an oxide layer directly contacting a second side of the free layer; wherein the tunnel barrier includes an oxide and has a first resistance-area (RA) product and the oxide layer has a second RA product that is lower than the first RA product. The MTJ may be included in a perpendicular spin torque transfer memory. The tunnel barrier and oxide layer form a memory having high stability with an RA product not substantively higher than a less stable memory having a MTJ with only a single oxide layer. Other embodiments are described herein.

Abstract translation: 实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的磁性隧道结（MTJ）; 所述隧道势垒直接接触所述自由层的第一侧; 和直接接触自由层的第二面的氧化物层; 其中所述隧道势垒包括氧化物并且具有第一电阻区域（RA）产物，并且所述氧化物层具有低于所述第一RA产物的第二RA产物。 MTJ可以包括在垂直旋转扭矩传递存储器中。 隧道势垒和氧化物层形成具有高稳定性的存储器，RA产物没有实质上高于具有仅具有单一氧化物层的MTJ的较不稳定的存储器。 本文描述了其它实施例。

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.