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    DIGITAL PREDISTORTION FOR DUAL-BAND POWER AMPLIFIERS
    23.
    发明申请
    DIGITAL PREDISTORTION FOR DUAL-BAND POWER AMPLIFIERS 有权
    双频功率放大器的数字预测

    公开(公告)号：US20160308577A1

    公开(公告)日：2016-10-20

    申请号：US15191583

    申请日：2016-06-24

    Applicant: Intel Corporation

    Inventor： Albert MOLINA ,  Kameran Azadet

    IPC: H04B1/62 ,  H04L27/36

    CPC classification number: H04B1/62 ,  G06F17/50 ,  G06F17/5009 ,  H03F1/3241 ,  H03F3/24 ,  H04B1/525 ,  H04J11/004 ,  H04L5/1461 ,  H04L25/03012 ,  H04L25/03343 ,  H04L27/367 ,  H04L27/368

    Abstract: A signal processing circuit arrangement may include a preamplifier circuit configured to map a first dimension input and a second dimension input to a first subset of a plurality of lookup table coefficients of a two-dimensional (2D) lookup table, wherein the first dimension input and the second dimension input each represent a signal level of one or more input signals, extrapolate from the first subset of the plurality of lookup table coefficients to generate a lookup table output, and apply the lookup table output to the one or more input signals to generate a predistorted input signal for an amplifier.

    Abstract translation: 信号处理电路装置可以包括前置放大器电路，其被配置为将第一维输入和第二维输入映射到二维（2D）查找表的多个查找表系数的第一子集，其中第一维输入和 所述第二尺寸输入各自表示一个或多个输入信号的信号电平，从所述多个查找表系数的所述第一子集外推，以产生查找表输出，并将所述查找表输出应用于所述一个或多个输入信号以产生 用于放大器的预失真输入信号。

    Method and system for digital equalization of a linear or non-linear system
    26.
    发明授权
    Method and system for digital equalization of a linear or non-linear system 有权

    公开(公告)号：US12206426B2

    公开(公告)日：2025-01-21

    申请号：US17358044

    申请日：2021-06-25

    Applicant: Intel Corporation

    Inventor： Albert Molina ,  Martin Clara ,  Kameran Azadet

    IPC: H03M1/00 ,  H03M1/06 ,  H03M1/10

    Abstract: A system and method for equalization of a linear or non-linear system. The system includes an adder configured to add an analog reference signal and an input signal, a processing system configured to process a sum of the analog reference signal and the input signal, a non-linear equalizer (NLEQ) configured to process an output of the processing system to remove a distortion incurred by the processing system, a calibration circuitry configured to generate a reconstructed reference signal in digital domain based on measurement of the analog reference signal, and generate coefficients for the NLEQ based on the reconstructed reference signal and the output of the processing system, and a subtractor configured to subtract the reconstructed reference signal from an output of the NLEQ. The analog reference signal may be a sinusoid including single or multiple tones of sinusoids. The non-linear system may be an analog-to-digital converter (ADC).

    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD
    27.
    发明公开
    PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD 审中-公开

    公开(公告)号：US20240345839A1

    公开(公告)日：2024-10-17

    申请号：US18647891

    申请日：2024-04-26

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Jeroen Leijten ,  Joseph Williams

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30079 ,  G06F9/3877 ,  G06F9/463 ,  G06F9/546

    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

    Processing pipeline with zero loop overhead
    29.
    发明授权
    Processing pipeline with zero loop overhead 有权

    公开(公告)号：US11989554B2

    公开(公告)日：2024-05-21

    申请号：US17131970

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Kameran Azadet ,  Jeroen Leijten ,  Joseph Williams

    IPC: G06F9/38 ,  G06F9/30 ,  G06F9/46 ,  G06F9/54

    CPC classification number: G06F9/30036 ,  G06F9/30079 ,  G06F9/3877 ,  G06F9/463 ,  G06F9/546

    Abstract: Techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. The processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. The described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. The described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

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