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    Embedded die flip-chip package assembly
    21.
    发明授权
    Embedded die flip-chip package assembly 有权

    公开(公告)号：US10128205B2

    公开(公告)日：2018-11-13

    申请号：US14199545

    申请日：2014-03-06

    Applicant: Intel Corporation

    Inventor： Thorsten Meyer ,  Sven Albers

    IPC: H01L23/02 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  G06F1/16 ,  H01L23/522 ,  H01L25/065 ,  H01L25/00 ,  H01L23/50

    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.

    Integrated circuit package having wirebonded multi-die stack
    25.
    发明授权
    Integrated circuit package having wirebonded multi-die stack 有权

    公开(公告)号：US12237305B2

    公开(公告)日：2025-02-25

    申请号：US17958298

    申请日：2022-09-30

    Applicant: INTEL CORPORATION

    Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

    IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L25/00 ,  H01L25/07

    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

    Method of embedding WLCSP components in E-WLB and E-PLB
    27.
    发明授权
    Method of embedding WLCSP components in E-WLB and E-PLB 有权

    公开(公告)号：US10147710B2

    公开(公告)日：2018-12-04

    申请号：US15982787

    申请日：2018-05-17

    Applicant: Intel Corporation

    Inventor： Vijay K. Nair ,  Thorsten Meyer

    IPC: H01L21/44 ,  H01L25/16 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L25/03 ,  H01L23/538

    Abstract: Embodiments of the invention include multi-die package and methods of making such multi-die packages. In an embodiment a mold layer has a first surface and a second surface that is opposite from the first surface. One or more first electrical components that each have a solderable terminal that is oriented to face the first surface of the mold layer. The mold layer may also have one or more second electrical components that each have a second type of terminal that is oriented to face the second surface of the mold layer. Embodiments may also include one or more conductive through vias formed between the first surface of the mold layer and the second surface of the mold layer. Accordingly an electrical connection may be made from the second surface of the mold layer to the first electrical components that are oriented to face the first surface of the mold layer.

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